Date:   Thu, 23 Feb 2023 17:28:34 +0000
From:   Mark Brown <broonie@kernel.org>
To:     Krishna Yarlagadda <kyarlagadda@nvidia.com>
Cc:     robh+dt@kernel.org, peterhuewe@gmx.de, jgg@ziepe.ca,
        jarkko@kernel.org, krzysztof.kozlowski+dt@linaro.org,
        linux-spi@vger.kernel.org, linux-tegra@vger.kernel.org,
        linux-integrity@vger.kernel.org, linux-kernel@vger.kernel.org,
        thierry.reding@gmail.com, jonathanh@nvidia.com,
        skomatineni@nvidia.com, ldewangan@nvidia.com
Subject: Re: [Patch V3 3/3] spi: tegra210-quad: Enable TPM wait polling
Message-ID: <Y/eiQg56fPn17uVf@sirena.org.uk>
References: <20230223162635.19747-1-kyarlagadda@nvidia.com>
 <20230223162635.19747-4-kyarlagadda@nvidia.com>
MIME-Version: 1.0
Content-Type: multipart/signed; micalg=pgp-sha512;
        protocol="application/pgp-signature"; boundary="O/f/GcIvq3/s+B+G"
Content-Disposition: inline
In-Reply-To: <20230223162635.19747-4-kyarlagadda@nvidia.com>
Precedence: bulk


--O/f/GcIvq3/s+B+G
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline

On Thu, Feb 23, 2023 at 09:56:35PM +0530, Krishna Yarlagadda wrote:

> Trusted Platform Module requires flow control. As defined in TPM
> interface specification, client would drive MISO line at same cycle as
> last address bit on MOSI.
> Tegra241 QSPI controller has TPM wait state detection feature which is
> enabled for TPM client devices reported in SPI device mode bits.
> Set half duplex flag for TPM device to detect and send entire message
> to controller in one shot.

I don't really understand what the controller is actually doing here, or
what the intended effect of the SPI_TPM_HW_FLOW flag is supposed to be.

>  	/* Enable Combined sequence mode */
>  	val = tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG);
> +	if (spi->mode & SPI_TPM_HW_FLOW) {
> +		if (tqspi->soc_data->tpm_wait_poll)
> +			val |= QSPI_TPM_WAIT_POLL_EN;
> +		else
> +			return -EIO;
> +	}

This just sets a bit in a register...

>  	val |= QSPI_CMB_SEQ_EN;
>  	tegra_qspi_writel(tqspi, val, QSPI_GLOBAL_CONFIG);
>  	/* Process individual transfer list */

...my guess is that setting that bit causes the individual transfers to
be delayed in completing without further changes?  Is is just some
transfers or all of them?

--O/f/GcIvq3/s+B+G
Content-Type: application/pgp-signature; name="signature.asc"

-----BEGIN PGP SIGNATURE-----

iQEzBAABCgAdFiEEreZoqmdXGLWf4p/qJNaLcl1Uh9AFAmP3okEACgkQJNaLcl1U
h9DS1wf7BuDUQOr/gwEv++44AI8XaJKX7ThTm1Yz7gSKfmjBnRMD2LZKvUW7KZgc
IG+5yLeW2ggZmqBeQ3nfYjXPWc0ONXA2wRoXie3VNeaMdY6/p/B+8C5cHFoQVVW2
C7CDtV/bPXmGHsY4cBmvkOjmQiOhFuNric9K+VJJxckJzqnnxviKPK+Qhm/Q7XQs
1xIQ19QcyaLDGjRYFWDNPXY8z9Q9CsW2S9gItlVvJ6Sg3WacIvAlqpzSXafF6nj6
TDqPE893T2X1D05QPJTteq6NqjLzz3Xd5Z5IanGhHDPoEnaTs2PDqSaRCG6//x9Q
qDVJFbKisNLIOR4Dk2W7m3qBTl0j3Q==
=QTUE
-----END PGP SIGNATURE-----

--O/f/GcIvq3/s+B+G--