From:   Krishna Yarlagadda <kyarlagadda@nvidia.com>
To:     Mark Brown <broonie@kernel.org>
CC:     "robh+dt@kernel.org" <robh+dt@kernel.org>,
        "peterhuewe@gmx.de" <peterhuewe@gmx.de>,
        "jgg@ziepe.ca" <jgg@ziepe.ca>,
        "jarkko@kernel.org" <jarkko@kernel.org>,
        "krzysztof.kozlowski+dt@linaro.org" 
        <krzysztof.kozlowski+dt@linaro.org>,
        "linux-spi@vger.kernel.org" <linux-spi@vger.kernel.org>,
        "linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org>,
        "linux-integrity@vger.kernel.org" <linux-integrity@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "thierry.reding@gmail.com" <thierry.reding@gmail.com>,
        Jonathan Hunter <jonathanh@nvidia.com>,
        Sowjanya Komatineni <skomatineni@nvidia.com>,
        Laxman Dewangan <ldewangan@nvidia.com>
Subject: RE: [Patch V3 3/3] spi: tegra210-quad: Enable TPM wait polling
Thread-Topic: [Patch V3 3/3] spi: tegra210-quad: Enable TPM wait polling
Thread-Index: AQHZR6OxGxF/RwO310KJcd4KIXk32a7cyTsAgAAUkWA=
Date:   Thu, 23 Feb 2023 18:46:22 +0000
Message-ID: <DM4PR12MB57696F6C2AB9217ADBE6FFE4C3AB9@DM4PR12MB5769.namprd12.prod.outlook.com>
References: <20230223162635.19747-1-kyarlagadda@nvidia.com>
 <20230223162635.19747-4-kyarlagadda@nvidia.com>
 <Y/eiQg56fPn17uVf@sirena.org.uk>
In-Reply-To: <Y/eiQg56fPn17uVf@sirena.org.uk>
Accept-Language: en-IN, en-US
Content-Language: en-US
x-ms-exchange-antispam-messagedata-chunkcount: 1
x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?7gTkwG1/PMpmYPWr27HfJdFAfOGEQFPdBV8axjSu9o+tIJ5ptN9kEbNjiHo0?=
 =?us-ascii?Q?6rXSwV9G2SZ3cvM/bO0YIf/SrcwiGaKt99AYVlr8J65gvYdsTz/S/hCeCpxX?=
 =?us-ascii?Q?GUZ7JGPGiK16heDlmWPrn5xNxdTDrV4fLIP2vqhlMM83uMJys6bfMstTbZPU?=
 =?us-ascii?Q?LkPgR+AZO3lAxQeB0hjgTJ76G+QTxnuXq2MvtM9zdpqUaeN/5Bb/f0a/cwRj?=
 =?us-ascii?Q?e3PjI+8p101D2vRnKXHQ7M99k8ZxVgluIJtxyORsCLfvC0ai27K+c1VkwogU?=
 =?us-ascii?Q?KGBm8ltaRiRxZvzOg9Pz1ikc7WArpucnkSpHxPljdJuHi0/LkL4C+jgPiD4w?=
 =?us-ascii?Q?kXtaHVWHf4jJx4oVldiyujJ/pBhaCwTUMx68b4gnIypMSYqop4euwJ7hxaa1?=
 =?us-ascii?Q?TbCebfwxpst52nUKZBLvY+SLUYxlBgifHeNDOWCltrjd7/gig+wO+Zz027eg?=
 =?us-ascii?Q?tEU52pvOua2uyc4vK55Jg9kM2iZF7eIYNlep19g5YMxMkfjkQR5npvoclVCy?=
 =?us-ascii?Q?dCLn9UL5JlqpnBsEadNK7A8nMIM8ltBQ//cRuwMSocFPRI+8JCv72tBPZ2FF?=
 =?us-ascii?Q?k76R2LBpvrCz6jeAqN+WX6i5ZweH0C2lOyGd+/+yqXStRTy+z8IKgBTq7gxO?=
 =?us-ascii?Q?Bg1w4G3wyLlQVFdcIEUZROtbd11B7mEMjLtfcPZ6Ee37q1ySi/GRRQkorC8f?=
 =?us-ascii?Q?Mi53JciXuwkBtYPj9Q7pS9luLDl/nbhxxeYnqbtv1vPXIFCGcGXrhOm8CEdD?=
 =?us-ascii?Q?ixekeMWUhZP0C6nb1IDXmb0MG2S6DgwyoRJ1nza0/k0zVZhxiLj+3np3u0N8?=
 =?us-ascii?Q?aRd80K86gPFb+JR6PxAFLJtyuoYMDq+MYUsGHkUk37G3v7bHLyHssgXayoaD?=
 =?us-ascii?Q?r96RzMQ6YWQf/XBV+U1iJ7iIK41Y5523JxFARLg0GFqiif/tf0s594J5Vud3?=
 =?us-ascii?Q?aKFc0fgXi1+iIRa/Jz9ESuoGaNLe/SuGWoyd4iD1uw+u3oJo0xcsqFK+vOfi?=
 =?us-ascii?Q?h25i0oQ6bzs1wBSp+7Kd4CnvIltrH/C2j2TGkLAbupT5YUUSJ8DNtGnWitHD?=
 =?us-ascii?Q?Q1fyG80F1sD7q15GdvgVJ5zYEvcaUs+r4VREkHKiLFvMQE8khlXZGNw+vRK+?=
 =?us-ascii?Q?6rDQi4t9BLBfFhXPOltwZ+movoPnD1OSlk7+MvlBMwHc9GcJYbTVOVsdikPY?=
 =?us-ascii?Q?8iYhM+LeMXJeHgL9P/Z+T+0mUFbhABJdx4eIYlxBSeeLGBPj/OVqIqE9qEc/?=
 =?us-ascii?Q?xKykEgSUeeVnG7go1MdCzyL3kLmJ7wX9yk3uLu63KxL8SliGENa19t1IuOuB?=
 =?us-ascii?Q?QR1u9NMfk5xY7PAK2ulNHd5U5+6dXZQHm5IfWq94I+CuYyY0UzhIJzdT2ahf?=
 =?us-ascii?Q?e3BOKgdKORB8oSKFOcG4v97QW0C+KEi815ciIocJNLOVD3GGqN/Jj51hEhwZ?=
 =?us-ascii?Q?uXXG9MUX9bLG+KlvSZ1p8OJAZogigmHTlsYIbtf5UymCVWOHGHce1jbP4nXw?=
 =?us-ascii?Q?TGYRS640rpHeKI4qEkLBVVFsF8ua/NroZ9/WP5Q+kh2J5Lr7E7R/sjTiK0Xj?=
 =?us-ascii?Q?rXfRmx3pAwP8570PRvX7ybuonUmgvZn6ftK/2llW?=
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: quoted-printable
MIME-Version: 1.0
X-OriginatorOrg: Nvidia.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-AuthSource: DM4PR12MB5769.namprd12.prod.outlook.com
X-MS-Exchange-CrossTenant-Network-Message-Id: c00e585a-8a37-4544-fc03-08db15ce429e
X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Feb 2023 18:46:22.7594
 (UTC)
X-MS-Exchange-CrossTenant-fromentityheader: Hosted
X-MS-Exchange-CrossTenant-id: 43083d15-7273-40c1-b7db-39efd9ccc17a
X-MS-Exchange-CrossTenant-mailboxtype: HOSTED
X-MS-Exchange-CrossTenant-userprincipalname: U7AwmAkRP1en6/ZOINULi/60v2VylImD26cpLLEZDMHw1v8VXBtnfyn3S3vakcR1c4Kcqkx5VOIEkh/LlqEEsw==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4392
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

> -----Original Message-----
> From: Mark Brown <broonie@kernel.org>
> Sent: 23 February 2023 22:59
> To: Krishna Yarlagadda <kyarlagadda@nvidia.com>
> Cc: robh+dt@kernel.org; peterhuewe@gmx.de; jgg@ziepe.ca;
> jarkko@kernel.org; krzysztof.kozlowski+dt@linaro.org; linux-
> spi@vger.kernel.org; linux-tegra@vger.kernel.org; linux-
> integrity@vger.kernel.org; linux-kernel@vger.kernel.org;
> thierry.reding@gmail.com; Jonathan Hunter <jonathanh@nvidia.com>;
> Sowjanya Komatineni <skomatineni@nvidia.com>; Laxman Dewangan
> <ldewangan@nvidia.com>
> Subject: Re: [Patch V3 3/3] spi: tegra210-quad: Enable TPM wait polling
>=20
> On Thu, Feb 23, 2023 at 09:56:35PM +0530, Krishna Yarlagadda wrote:
>=20
> > Trusted Platform Module requires flow control. As defined in TPM
> > interface specification, client would drive MISO line at same cycle as
> > last address bit on MOSI.
> > Tegra241 QSPI controller has TPM wait state detection feature which is
> > enabled for TPM client devices reported in SPI device mode bits.
> > Set half duplex flag for TPM device to detect and send entire message
> > to controller in one shot.
>=20
> I don't really understand what the controller is actually doing here, or
> what the intended effect of the SPI_TPM_HW_FLOW flag is supposed to be.
>=20
> >  	/* Enable Combined sequence mode */
> >  	val =3D tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG);
> > +	if (spi->mode & SPI_TPM_HW_FLOW) {
> > +		if (tqspi->soc_data->tpm_wait_poll)
> > +			val |=3D QSPI_TPM_WAIT_POLL_EN;
> > +		else
> > +			return -EIO;
> > +	}
>=20
> This just sets a bit in a register...
>=20
> >  	val |=3D QSPI_CMB_SEQ_EN;
> >  	tegra_qspi_writel(tqspi, val, QSPI_GLOBAL_CONFIG);
> >  	/* Process individual transfer list */
>=20
> ...my guess is that setting that bit causes the individual transfers to
> be delayed in completing without further changes?  Is is just some
> transfers or all of them?
TPM spec define flow control over SPI.  TPM device/client inserts
wait state on MISO line when address is transferred on MOSI. This state
has to be detected by reading the MISO line which needs full duplex
transfer during address phase. Tegra QSPI controller can only support
half duplex. But in combined sequence mode, it can detect wait state
inserted by TPM device and send or receive data when device is ready.
Detection happens on all transfers with TPM.