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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT059.mail.protection.outlook.com (10.13.174.160) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6134.21 via Frontend Transport; Thu, 23 Feb 2023 21:07:57 +0000 Received: from AUS-LX-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Thu, 23 Feb 2023 15:07:55 -0600 From: Mario Limonciello To: , Andreas Noever , Michael Jamet , "Yehezkel Bernat" CC: , Mario Limonciello , , Subject: [PATCH v4 1/3] thunderbolt: Adjust how NVM reading works Date: Thu, 23 Feb 2023 15:07:41 -0600 Message-ID: <20230223210743.9819-2-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230223210743.9819-1-mario.limonciello@amd.com> References: <20230223210743.9819-1-mario.limonciello@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT059:EE_|BY5PR12MB4871:EE_ X-MS-Office365-Filtering-Correlation-Id: 49c94f7b-14bd-43a4-0f54-08db15e209d8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Feb 2023 21:07:57.3441 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 49c94f7b-14bd-43a4-0f54-08db15e209d8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT059.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4871 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some TBT3 devices have a hard time reliably responding to bit banging requests correctly when connected to AMD USB4 hosts running Linux. These problems are not reported in any other CM supported on AMD platforms, and comparing the Windows and Pre-OS implementations the Linux CM is the only one that utilizes bit banging to access the DROM. Other CM implementations access the DROM directly from the NVM instead of bit banging. Adjust the flow to use this method to fetch the NVM when the downstream device has an LC that can be used to fetch the UUID later. The bit banging method will only be used if this has failed or no LC is present. Signed-off-by: Mario Limonciello --- v3->v4: * Don't run code for USB4 devices v2->v3: * Split out refactor v1->v2: * Update commit message to indicate which CMs are tested * Adjust flow to only fetch DROM from NVM on TBT3 and bit bang on TBT1/2 --- drivers/thunderbolt/eeprom.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/thunderbolt/eeprom.c b/drivers/thunderbolt/eeprom.c index c90d22f56d4e..8c9e553e2fca 100644 --- a/drivers/thunderbolt/eeprom.c +++ b/drivers/thunderbolt/eeprom.c @@ -640,6 +640,11 @@ int tb_drom_read(struct tb_switch *sw) return 0; } + /* We can use LC to get UUID later */ + if (sw->cap_lc && !tb_switch_is_usb4(sw) && + tb_drom_copy_nvm(sw, &size) == 0) + goto parse; + res = tb_drom_read_n(sw, 14, (u8 *) &size, 2); if (res) return res; -- 2.34.1