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References: <20230223134345.82625-1-angelogioacchino.delregno@collabora.com>
In-Reply-To: <20230223134345.82625-1-angelogioacchino.delregno@collabora.com>
From:   Chen-Yu Tsai <wenst@chromium.org>
Date:   Fri, 24 Feb 2023 17:41:52 +0800
Message-ID: <CAGXv+5HvQugnQjJbdqOuQKeqpFgJOvtzzwhVD9FL2CKgxxJYQQ@mail.gmail.com>
Subject: Re: [PATCH v2 00/16] Enable GPU with DVFS support on MediaTek SoCs
To:     AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@collabora.com>
Cc:     matthias.bgg@gmail.com, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-mediatek@lists.infradead.org
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On Thu, Feb 23, 2023 at 9:43 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> Changes in v2:
>  - Changed MT8186 to use only two power domains for the GPU.
>
> We finally have working GPU DVFS on MediaTek SoCs.
> On Panfrost.
> For real.
> ...and the best part is that it's going upstream.
>
> In order to get GPU DVFS working, it was necessary to satisfy a
> specific constraint (which is different, depending on the SoC)
> between two regulators: GPU VCORE and GPU SRAM.
> This was done through adding the mtk-regulator-coupler driver,
> which transparently manages the voltage relation between these
> two vregs, hence completely eliminating the need to manage these
> regulators in the Panfrost driver; this solves the long standing
> issue with devfreq+opp tables not supporting managing voltages
> for two regulators per opp entry out of the box, due to which
> we never got GPU DVFS on those SoCs, often locking them out to
> a low GPU frequency.
>
> This changes. Right now!
>
> Tested on MT8192, MT8195 Chromebooks.
>
> This series depends on [1].
>
> [1]: https://lore.kernel.org/lkml/20230223133440.80941-1-angelogioacchino=
.delregno@collabora.com/
>
> Alyssa Rosenzweig (2):
>   arm64: dts: mediatek: mt8192: Add GPU nodes
>   arm64: dts: mediatek: mt8192-asurada: Enable GPU
>
> AngeloGioacchino Del Regno (13):
>   arm64: dts: mediatek: mt8183-kukui: Couple VGPU and VSRAM_GPU
>     regulators
>   arm64: dts: mediatek: mt8183-kukui: Override vgpu/vsram_gpu
>     constraints
>   arm64: dts: mediatek: mt8183: Remove second opp-microvolt entries from
>     gpu table
>   arm64: dts: mt8183-pumpkin: Couple VGPU and VSRAM_GPU regulators
>   arm64: dts: mediatek: mt8183-evb: Couple VGPU and VSRAM_GPU regulators
>   arm64: dts: mediatek: mt8183: Use mediatek,mt8183b-mali as GPU
>     compatible
>   arm64: dts: mediatek: mt8192: Add mfg_ref_sel clock to MFG0 domain
>   arm64: dts: mediatek: mt8192-asurada: Assign sram supply to MFG1 pd
>   arm64: dts: mediatek: mt8192-asurada: Couple VGPU and VSRAM_OTHER
>     regulators
>   arm64: dts: mediatek: mt8195: Add mfg_core_tmp clock to MFG1 domain
>   arm64: dts: mt8195: Add panfrost node for Mali-G57 Valhall Natt GPU
>   arm64: dts: mediatek: mt8195-cherry: Enable Mali-G57 GPU
>   arm64: dts: mediatek: mt8186: Add GPU node
>
> N=C3=ADcolas F. R. A. Prado (1):
>   arm64: dts: mediatek: mt8192-asurada: Add MFG0 domain supply

Tested-by: Chen-Yu Tsai <wenst@chromium.org>

on MT8183 Juniper, MT8192 Hayato, MT8195 Tomato, MT8186 not-yet-upstreamed
device.