MIME-Version: 1.0
References: <20230223134345.82625-1-angelogioacchino.delregno@collabora.com> <20230223134345.82625-10-angelogioacchino.delregno@collabora.com>
In-Reply-To: <20230223134345.82625-10-angelogioacchino.delregno@collabora.com>
From:   Chen-Yu Tsai <wenst@chromium.org>
Date:   Fri, 24 Feb 2023 17:57:37 +0800
Message-ID: <CAGXv+5EtbMtDTwXvOqGBSNXPF4z88F-Hr0M5=PW+JeV4i_YYng@mail.gmail.com>
Subject: Re: [PATCH v2 09/16] arm64: dts: mediatek: mt8192-asurada: Add MFG0
 domain supply
To:     AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@collabora.com>
Cc:     matthias.bgg@gmail.com, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-mediatek@lists.infradead.org,
        =?UTF-8?B?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= 
        <nfraprado@collabora.com>
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
Precedence: bulk

On Thu, Feb 23, 2023 at 9:44 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> From: N=C3=ADcolas F. R. A. Prado <nfraprado@collabora.com>
>
> The mfg0 power domain encompasses the whole GPU and its surrounding
> glue logic. This power domain has a separate power rail.
>
> Add its power supply for Asurada.
>
> Signed-off-by: N=C3=ADcolas F. R. A. Prado <nfraprado@collabora.com>
> [wenst@chromium.org: fix subject prefix and add commit message]
> Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
> [Angelo: Reordered commits to address DVFS stability issues]
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@coll=
abora.com>

Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>