From:   Ravi Gunasekaran <r-gunasekaran@ti.com>
To:     <nm@ti.com>, <afd@ti.com>, <vigneshr@ti.com>, <kristo@kernel.org>,
        <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
        <s-vadapalli@ti.com>, <vaishnav.a@ti.com>, <r-gunasekaran@ti.com>
CC:     <linux-arm-kernel@lists.infradead.org>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH v11 8/8] arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIe
Date:   Fri, 24 Feb 2023 15:54:38 +0530
Message-ID: <20230224102438.6541-9-r-gunasekaran@ti.com>
In-Reply-To: <20230224102438.6541-1-r-gunasekaran@ti.com>
References: <20230224102438.6541-1-r-gunasekaran@ti.com>
MIME-Version: 1.0
Content-Type: text/plain
Precedence: bulk

From: Aswath Govindraju <a-govindraju@ti.com>

x1 lane PCIe slot in the common processor board is enabled and connected to
J721S2 SOM. Add PCIe DT node in common processor board to reflect the
same.

Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
---
Changes from v10:
* Removed Link tag from commit message

Changes from v9:
* No change

Changes from v8:
* No change

Changes from v7:
* No change

Changes from v6:
* Removed pcie_ep node update

Changes from v5:
* No change

Changes from v4:
* No change

Changes from v3:
* No change

Changes from v2:
* Patch newly added to the series

 arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index 76b420379645..b195f250891a 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -386,6 +386,14 @@
 	};
 };
 
+&pcie1_rc {
+	status = "okay";
+	reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
+	phys = <&serdes0_pcie_link>;
+	phy-names = "pcie-phy";
+	num-lanes = <1>;
+};
+
 &mcu_mcan0 {
 	status = "okay";
 	pinctrl-names = "default";
-- 
2.17.1