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b=Zc9FRaVKCcJgCNP6TKkobSOHdidTWtS9U3MxDPou/jXfGZWIYhK0QGIYNKgnMHMY6PdfPkn3mZp15T6Lc4E7SarKwZ2iQssUeMp+bvSEDPncidLYfoi20UxHUTzTI1u1hPLVBN4s6TAq7YQNM04O612jy8yzmAEk6SPcvE+fbmY= Received: from VI1PR04MB4222.eurprd04.prod.outlook.com (2603:10a6:803:46::19) by DU2PR04MB8567.eurprd04.prod.outlook.com (2603:10a6:10:2d6::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6134.24; Fri, 24 Feb 2023 10:56:23 +0000 Received: from VI1PR04MB4222.eurprd04.prod.outlook.com ([fe80::8562:affc:e0c:c610]) by VI1PR04MB4222.eurprd04.prod.outlook.com ([fe80::8562:affc:e0c:c610%7]) with mapi id 15.20.6134.024; Fri, 24 Feb 2023 10:56:22 +0000 From: Chancel Liu To: Mark Brown CC: "lgirdwood@gmail.com" , "robh+dt@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "perex@perex.cz" , "tiwai@suse.com" , "ckeepax@opensource.cirrus.com" , "patches@opensource.cirrus.com" , "alsa-devel@alsa-project.org" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" Subject: RE: Re: [PATCH 2/4] ASoC: dt-bindings: wlf,wm8524: Add a property to specify power up sequency time Thread-Topic: Re: [PATCH 2/4] ASoC: dt-bindings: wlf,wm8524: Add a property to specify power up sequency time Thread-Index: AQHZSD6iKP3DVcsE70eUS5M7nhJXLA== Date: Fri, 24 Feb 2023 10:56:22 +0000 Message-ID: References: <20230222113945.3390672-1-chancel.liu@nxp.com> <20230222113945.3390672-2-chancel.liu@nxp.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB4222.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: c7fcf3ff-6fe2-4b59-a5c5-08db1655c48e X-MS-Exchange-CrossTenant-originalarrivaltime: 24 Feb 2023 10:56:22.8146 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: XNuG9SfGHaaOrVKGkkaCU+7QWHWKtBsw0/4Z4jDCpPhGxv8JIHevJPhIVUToZVeA8aw/70wudWL+Iwd+4m4vPA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR04MB8567 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > On Wed, Feb 22, 2023 at 07:39:43PM +0800, Chancel Liu wrote: > > This property specifies power up to audio out time. It's necessary > > beacause this device has to wait some time before ready to output > > audio after MCLK, BCLK and MUTE=3D1 are enabled. For more details about > > the timing constraints, please refer to WTN0302 on > > https://www.cirrus.com/products/wm8524/ >=20 > According to that the delay is a property of MCLK and the sample rate rat= her > than a per board constant, it shouldn't be in DT but rather the driver sh= ould > figure out the required delay on each startup. I can't agree with you more. From the power up to audio out timing table in WTN0302, the delay depends on sample rate and MCLK. Driver should calculate= it rather than read it from DT. However as I mentioned in my last email, value= s in the table seem not accurate for all systems. It's a kind of compromise to g= et the value from DT. Do other codecs have a similar situation? Thank you very much for your suggestions! Regards,=20 Chancel Liu