Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B92FC678DB for ; Fri, 24 Feb 2023 13:51:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229711AbjBXNvd (ORCPT ); Fri, 24 Feb 2023 08:51:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43560 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229456AbjBXNva (ORCPT ); Fri, 24 Feb 2023 08:51:30 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9A99B6798C; Fri, 24 Feb 2023 05:51:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1677246689; x=1708782689; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=gL3Cs2+m/4fshHcUNF4uRlCTHPwu5XQNW/5CYVP3NRU=; b=yBFHIfqd0nQ/NWJU0wg3ClHM1oBUl4GrQWsGmQAhU956NVXP0k78AYpE smqOmzw6DHy0005r57Mb9gCD2dE1dgaSn5OAu/4+0IM3w+pPn+fKVGxeZ m1ODFWLVp1dcWf7JbsBqGgF1Yrjc69uqDQ/Ap1tpbUCUKQh6R2a4qZmZ5 dPVH8+U6NqV/ackLOkOnJk67JIekh+gg1sHFHNFBx4zQVFY12GrN+XzYf II2vq6qsm3NV7jebOPqB1B8VmdH5eAr4TFM0ZmeHxhKs7mPwDar74aX2x tjAWXjyokUXgzRE472gAOsSs9ZYZ7FdOsKcK7hxkLc11PJW11gc6d4ZgG A==; X-IronPort-AV: E=Sophos;i="5.97,324,1669100400"; d="scan'208";a="138923417" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 24 Feb 2023 06:51:28 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Fri, 24 Feb 2023 06:51:24 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.16 via Frontend Transport; Fri, 24 Feb 2023 06:51:21 -0700 From: Conor Dooley To: CC: Conor Dooley , , "Miguel Ojeda" , Alex Gaynor , "Wedson Almeida Filho" , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , "Nathan Chancellor" , Nick Desaulniers , Tom Rix , , , , Subject: [RFC RESEND 0/2] RISC-V: enable rust Date: Fri, 24 Feb 2023 13:50:42 +0000 Message-ID: <20230224135044.2882109-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1608; i=conor.dooley@microchip.com; h=from:subject; bh=gL3Cs2+m/4fshHcUNF4uRlCTHPwu5XQNW/5CYVP3NRU=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDMk/DqyX/be4ynaJ06921nXKl9tk5qT9mD3X4ciGE9WnXQoS j77z7yhlYRDjYJAVU2RJvN3XIrX+j8sO5563MHNYmUCGMHBxCsBEoqsY/ucUZijfbD/GaTebVVrZwG PNqjed5778FN916Yi6WqpH+ndGhpUu9zVn9TZPebhcMPv6pm+CzSc8eFpXTAjz/PnG9P/ZaSwA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This is a somewhat blind (and maybe foolish) attempt at enabling Rust for RISC-V. I've tested this on Icicle, and the modules seem to work. I'd like to play around with Rust on RISC-V, but I'm not interested in using downstream kernels, so figured I should try and see what's missing... I've tagged this as RFC in case I've missed some "WAaaaa you can't do this" somewhere :) Thanks, Conor. Changes in RFC-RESEND: - fixed the asymmetrical additions in the Makefile bits - added cc-cover to my git send-email command... CC: Miguel Ojeda CC: Alex Gaynor CC: Wedson Almeida Filho CC: Boqun Feng CC: Gary Guo CC: Björn Roy Baron CC: Jonathan Corbet CC: Paul Walmsley CC: Palmer Dabbelt CC: Nathan Chancellor CC: Nick Desaulniers CC: Tom Rix CC: rust-for-linux@vger.kernel.org CC: linux-doc@vger.kernel.org CC: linux-kernel@vger.kernel.org CC: linux-riscv@lists.infradead.org CC: llvm@lists.linux.dev Miguel Ojeda (2): scripts: generate_rust_target: enable building on RISC-V RISC-V: enable building the 64-bit kernels with rust support Documentation/rust/arch-support.rst | 2 ++ arch/riscv/Kconfig | 1 + arch/riscv/Makefile | 3 ++- scripts/generate_rust_target.rs | 19 +++++++++++++++++++ 4 files changed, 24 insertions(+), 1 deletion(-) -- 2.39.2