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Fri, 24 Feb 2023 07:49:59 -0800 From: Krishna Yarlagadda To: , , , , , , , , , CC: , , , , Krishna Yarlagadda Subject: [Patch V4 3/3] spi: tegra210-quad: set half duplex flag Date: Fri, 24 Feb 2023 21:19:41 +0530 Message-ID: <20230224154941.68587-4-kyarlagadda@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230224154941.68587-1-kyarlagadda@nvidia.com> References: <20230224154941.68587-1-kyarlagadda@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT061:EE_|CY8PR12MB7729:EE_ X-MS-Office365-Filtering-Correlation-Id: 9ca6ab6c-dbb9-43f1-b0e9-08db167ed175 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 1UqUkIAo4S7/DdioFOd0C8fxdYvwS/t9m0TqNI4kqX3SLsNYio37WJxhZObSKJDH+aH9n90lMXpiWY+lFXyixz8xD9DwPmbujjrvFpdraqx5EopUdPH1b08SER66jw+nSJam+SAlOMevs/4pKS194zFgAAn51DRiWvYlaCzdA4CpR3mq3XVdquC/cJOtmtSajoyDt/aA3t7wbEFW6tPzWBLvYdcHv1YUE0BE6AyHeCEMzKFPscR5oI/mYmBzdfolnR1e8n40fDcihG8mtfc775KwD5BPeveZyt6H/1BkvRRQ3LCvuqOwMqnvAtSgcBkBYTmrRrtjrwwL7oyFic78MuDz+GtxoWIxoYNvCdoOTbNWMYiignmMu4EOR0fvq4cU8SGh9lXAqMHWJ2OxDp2wC3bAQoWE0qCb2WdwbFlgsN6bRhrTV8Q3V/mMRhSFuumkDjDZP4G8Nr9G5JcIecNEShOVGEIechBp7jsQqLVLgbAEQHBSjjJdzrKFfq1JX3zIzEYZAuNWwq27NSt8GViU7CAicwg1weeIgbtGmyWLCa++EX1/5nCefmkCekgtevhRqgUcYzTASiiUA3ILFNXVbAjDOk55yy3cNC6TAxaDA/GdiXyEARS4MVm5rpZKYNQxuIU4JxfR6V3UOXixXqSY7k0OIZ2F6Ha38X08sgTgrz44mjoGWt17psH2pjolzst4Dun2CjgBCy4/aAdH8euyBHXlMzoFeOCN/kGlFOeHuxNtKzU4EaPsuqDZlBVK0A8/1o057p7iatoKJuXpDthfvg6SZmaFRdyI5zhrXfO7SsL56YWWakkWMMS6jufH5mvTBF1XKxEF5KB7JV1jG4gWmQ== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230025)(4636009)(376002)(346002)(136003)(39860400002)(396003)(451199018)(5400799012)(46966006)(40470700004)(36840700001)(83380400001)(41300700001)(426003)(34020700004)(47076005)(36860700001)(70586007)(70206006)(8676002)(4326008)(82740400003)(316002)(186003)(36756003)(26005)(336012)(8936002)(7636003)(54906003)(110136005)(2616005)(5660300002)(82310400005)(7416002)(40460700003)(921005)(356005)(86362001)(7696005)(478600001)(4744005)(2906002)(40480700001)(107886003)(1076003)(6666004)(83996005)(2101003)(12100799015);DIR:OUT;SFP:1501; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Feb 2023 15:50:13.7492 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9ca6ab6c-dbb9-43f1-b0e9-08db167ed175 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT061.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7729 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Tegra QSPI controller only supports half duplex transfers. Set half duplex constrain flag. Signed-off-by: Krishna Yarlagadda --- drivers/spi/spi-tegra210-quad.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c index 39dec2dc161b..fe15fa6eecd1 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -1553,6 +1553,7 @@ static int tegra_qspi_probe(struct platform_device *pdev) master->mode_bits = SPI_MODE_0 | SPI_MODE_3 | SPI_CS_HIGH | SPI_TX_DUAL | SPI_RX_DUAL | SPI_TX_QUAD | SPI_RX_QUAD; master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | SPI_BPW_MASK(8); + master->flags = SPI_CONTROLLER_HALF_DUPLEX; master->setup = tegra_qspi_setup; master->transfer_one_message = tegra_qspi_transfer_one_message; master->num_chipselect = 1; -- 2.17.1