Date:   Sat, 25 Feb 2023 23:49:47 +0100
From:   Alexandre Belloni <alexandre.belloni@bootlin.com>
To:     Jack Chen <zenghuchen@google.com>
Cc:     linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org,
        Jesus Sanchez-Palencia <jesussanp@google.com>,
        Mark Slevinsky <markslevinsky@google.com>
Subject: Re: [PATCH v3] i3c: update dw-i3c-master i3c_clk_cfg function
Message-ID: <167736537001.623134.2161286183992135167.b4-ty@bootlin.com>
References: <20230216151057.293764-1-zenghuchen@google.com>
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On Thu, 16 Feb 2023 10:10:57 -0500, Jack Chen wrote:
> Bus-speed could be default(12.5MHz) or defined by users in dts.
> Dw-i3c-master should not hard-code the initial speed to be
> I3C_BUS_TYP_I3C_SCL_RATE (12.5MHz)
> And because of Synopsys's I3C controller limit (hcnt/lcnt register
> length) and core-clk provided, there is a limit to bus speed, too.
> For example, when core-clk is 250 MHz, the bus speed cannot be
> lowered below 1MHz.
> 
> [...]

Applied, thanks!

[1/1] i3c: update dw-i3c-master i3c_clk_cfg function
      commit: 07eac9c306a0efd73a43804b50c88c67696a3c74

Best regards,

-- 
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com