Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4547AC7EE2E for ; Sun, 26 Feb 2023 21:57:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229582AbjBZV4H (ORCPT ); Sun, 26 Feb 2023 16:56:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51416 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229489AbjBZV4F (ORCPT ); Sun, 26 Feb 2023 16:56:05 -0500 Received: from mail-yw1-x112d.google.com (mail-yw1-x112d.google.com [IPv6:2607:f8b0:4864:20::112d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0EF4310A81 for ; Sun, 26 Feb 2023 13:55:59 -0800 (PST) Received: by mail-yw1-x112d.google.com with SMTP id 00721157ae682-536cd8f6034so126708057b3.10 for ; Sun, 26 Feb 2023 13:55:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=S1XNm1/M544VYpIKBT1XuxC0dGIFyRYPhVkkHQ5CpOg=; b=lEmOzoDLoYxVfNmrZRPZI0B1v7C/pE77zNsubm7hYTvY+iOLvoKN1UQ5gKeigOjgp/ R90wdm22e7JFbQlO0Gm6AlhXVcFRh3c/P7qkuRmG2tcU4uOseLsGkmnXmVv5ihDCpoSp q1ho/Bpr9CKyCk8fxYV9FwAx7ZpEvJoUU/yOeNRuyGGujjBzAsYShJxQ/rCGEzeTYXs3 20E2dc8GBh+EKBQVzJ3WYgI5UPSIFNEJ6TDecxGbTWz7cOhn8EBlTAj0gu7RvCq4Yk1d AE/OnOBiuo7ebamjDsBD+H8JC0oxrVBSFJYQtGZbcJaTqRYVDC5K46p4ISzTXkGi0CJj aPbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=S1XNm1/M544VYpIKBT1XuxC0dGIFyRYPhVkkHQ5CpOg=; b=CdK2/bsd/957N9WEIeIERtvunPVJND8qtBdg/kqkdR522F7YNen+TX1zQWYzxuNS3b /3K0NqAnCkIoUCWBdMbOwSQpkKdyZ9XbgYQEBYn4BYjhKWIJ1hXseuMRlvthXS3XGAl/ KyQMI4hzbE/5UWpjXJN8k8dJe7cBgeEZYYrPHuConrhgTAVtltrvdWHZ7cwKFwVOrpEf V0+7ZB4pYjHhmL1blsiChmCNVZ4jpLbzUuSW6tkyg01T4UD+Ivfem4wPJ9341F7iEDo9 iUEhhA1pKGIFyy5at5QVQmSgAFB+/1aIgUe+0sqUsGMgQ3jt8uPZy9EXs7HKN4Kz32U3 DJnA== X-Gm-Message-State: AO0yUKUXQJwvRJYO7lP2sLQlBhij4A907WraTwUDOwk0q07Ewls2VHeJ W1PrzlzCsWyuz0k2rN1nhxn1LVYWJTxL1qcC8WbojQ== X-Google-Smtp-Source: AK7set9UhdCKKcO9s5hy/11dL/IAO+MtPp+skSmgBmGc/y7Jt/pfPxiOLnPmpqz+8iTRbacTA8Q0RV6trhAMsj25IBk= X-Received: by 2002:a25:97c6:0:b0:9fc:e3d7:d60f with SMTP id j6-20020a2597c6000000b009fce3d7d60fmr6088583ybo.5.1677448558077; Sun, 26 Feb 2023 13:55:58 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Linus Walleij Date: Sun, 26 Feb 2023 22:55:46 +0100 Message-ID: Subject: Re: Regression in probing some AMBA devices possibly devlink related To: Saravana Kannan Cc: Linux ARM , linux-kernel , Ulf Hansson , Android Kernel Team Content-Type: multipart/mixed; boundary="0000000000006f555d05f5a16da3" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --0000000000006f555d05f5a16da3 Content-Type: text/plain; charset="UTF-8" On Sun, Feb 26, 2023 at 12:56 AM Saravana Kannan wrote: > On Sat, Feb 25, 2023 at 6:29 AM Linus Walleij wrote: > > > > Hi Saravana, > > > > I have a boot regression for Ux500 on mainline, but bisecting mainline > > isn't quite working for misc reasons :/ > > > > I'm not sure about this regression, but it smells like devlink-related. > > > > Ux500 have a bunch of normal and some AMBA devices. After > > boot this happens and we hang waiting for rootfs (which is on eMMC): > > Hmmm... my recent changes were definitely tested on systems with AMBA > devices and it worked. Some of them work, such as the TWD, interrupt controller GIC and the CoreSight stuff. > > [ 31.849586] amba 80126000.mmc: deferred probe pending > > [ 31.854801] amba 80118000.mmc: deferred probe pending > > [ 31.859895] amba 80005000.mmc: deferred probe pending > > [ 31.870297] amba 80120000.uart: deferred probe pending > > [ 31.875472] amba 80121000.uart: deferred probe pending > > [ 31.880689] amba 80004000.i2c: deferred probe pending > > [ 31.885799] amba 80128000.i2c: deferred probe pending > > [ 31.890932] amba 80110000.i2c: deferred probe pending > > [ 51.688361] vmem_3v3: disabling > > What does /debug/devices_deferred say about these? That should tell us > exactly what's blocking it. Can't get to check that sadly, because the root fs is on eMMC and that one is deferring indefinitely. I tried to compile in an initramfs but that became too big for this target. I'll check if I can use that on another target which I can boot directly from RAM. > Also if you convert all the pr_debug and dev_dbg in > drivers/base/core.c that should give us enough of an idea of what's > happening. Can you do that too and send it as an attachment (I logs > are hard to read when they get word wrapped)? This I could do! See attachment. It seems these devices are waiting for the PRCC reset-controller which is in drivers/clk/ux500/reset-prcc.c Very well! I went into arch/arm/boot/dts/ste-dbx5x0.dtsi and commented out all "resets = < &prcc....>; statements, and indeed then the system comes up fine! (The resets are not vital to boot the system.) But this is weird because the driver for the resets is spawn from the same device node that is spawning the clocks... All resources (clocks and resets) are spawn from here: drivers/clk/ux500/u8500_of_clk.c From these nodes in the DTS arch/arm/boot/dts/ste-dbx5x0.dtsi: clocks { compatible = "stericsson,u8500-clks"; /* * Registers for the CLKRST block on peripheral * groups 1, 2, 3, 5, 6, */ reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>, <0x8000f000 0x1000>, <0xa03ff000 0x1000>, <0xa03cf000 0x1000>; prcmu_clk: prcmu-clock { #clock-cells = <1>; }; prcc_pclk: prcc-periph-clock { #clock-cells = <2>; }; prcc_kclk: prcc-kernel-clock { #clock-cells = <2>; }; prcc_reset: prcc-reset-controller { #reset-cells = <2>; }; rtc_clk: rtc32k-clock { #clock-cells = <0>; }; smp_twd_clk: smp-twd-clock { #clock-cells = <0>; }; clkout_clk: clkout-clock { /* Cell 1 id, cell 2 source, cell 3 div */ #clock-cells = <3>; }; }; So it seems like the device core things that the resets are never coming online. But they are! I put some debug prints into the PRCC reset driver to make sure. diff --git a/drivers/clk/ux500/reset-prcc.c b/drivers/clk/ux500/reset-prcc.c index f7e48941fbc7..b1ed9a48cdfb 100644 --- a/drivers/clk/ux500/reset-prcc.c +++ b/drivers/clk/ux500/reset-prcc.c @@ -178,4 +178,6 @@ void u8500_prcc_reset_init(struct device_node *np, struct u8500_prcc_reset *ur) ret = reset_controller_register(rcdev); if (ret) pr_err("PRCC failed to register reset controller\n"); + + pr_info("PRCC reset controller registered\n"); } [ 0.000000] PRCC reset controller registered It is registered as early as the clocks. So it seems something is fishy with the reset resource resolution? > > The last regulator (vmem_3v3) is something the eMMC that didn't > > probe was supposed to use. > > > > All the failing drivers are AMBA PrimeCell devices: > > drivers/mmc/host/mmci.c > > drivers/tty/serial/amba-pl011.c > > drivers/i2c/busses/i2c-nomadik.c > > > > This makes me suspect something was done for ordinary (platform) > > devices that didn't happen for AMBA devices? > > > > This is the main portion of the device tree containing these > > devices and their resources: > > arch/arm/boot/dts/ste-dbx5x0.dtsi > > I'll take a closer look on Monday. Btw, I always prefer the dts file > because there's always some property that adds a dependency and that > might be the clue to whatever is broken. But I'll take a look at this. The top level DTS for this system I'm testing on (source for the log) is arch/arm/boot/dts/ste-ux500-samsung-golden.dts > It's unlikely the patch attached might fix it, but can you give it a shot? Sadly does not help! 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