Message-ID: <0c17dd26-b1aa-54b0-6dc4-561cd996cead@quicinc.com>
Date:   Mon, 27 Feb 2023 11:14:33 +0800
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Subject: Re: [PATCH v2 4/7] scsi: ufs: core: Add hwq print for debug
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To:     =?UTF-8?B?UG93ZW4gS2FvICjpq5jkvK/mlocp?= <Powen.Kao@mediatek.com>,
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References: <20230222030427.957-1-powen.kao@mediatek.com>
 <20230222030427.957-5-powen.kao@mediatek.com>
 <1b9c2bc9-a349-062a-597c-336804c05394@quicinc.com>
 <74bedcff32df0c93c14b004814017f3344247528.camel@mediatek.com>
From:   Ziqi Chen <quic_ziqichen@quicinc.com>
In-Reply-To: <74bedcff32df0c93c14b004814017f3344247528.camel@mediatek.com>
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Hi  Powen,

The Bao. D . Nguyen (quic_nguyenb@quicinc.com) from QCOM already made 
patch to support MCQ abort.

++ Bao here to be aware of it in case your error handing patch conflict 
with his abort handling patch.


Best Regards,

Ziqi


On 2/23/2023 10:13 PM, Powen Kao (高伯文) wrote:
> Hi Ziqi,
>
> Thanks for ur comments.
>
> This piece of code successfully dump relevent registers on our
> platform. As you know, mcq error handling flow is not ready yet so the
> insertion point might not seems to be reasonable.
>
> Maybe drop this patch for now, I will send it later with error handling
> patches.
>
>
> On Thu, 2023-02-23 at 18:14 +0800, Ziqi Chen wrote:
>> Hi Po-Wen,
>>
>> On 2/22/2023 11:04 AM, Po-Wen Kao wrote:
>>> +void ufshcd_mcq_print_hwqs(struct ufs_hba *hba, unsigned long
>>> bitmap)
>>> +{
>>> +	int id, i;
>>> +	char prefix[15];
>>> +
>>> +	if (!is_mcq_enabled(hba))
>>> +		return;
>>> +
>>> +	for_each_set_bit(id, &bitmap, hba->nr_hw_queues) {
>>> +		snprintf(prefix, sizeof(prefix), "q%d SQCFG: ", id);
>>> +		ufshcd_hex_dump(prefix,
>>> +			hba->mcq_base + MCQ_QCFG_SIZE * id,
>>> MCQ_QCFG_SQ_SIZE);
>> Is your purpose dump per hardware queue registers here?  If yes, why
>> don't use ufsmcq_readl() to save to a buffer and then use
>> ufshcd_hex_dump()
>>
>> to dump ? Are you sure ufshcd_hex_dump() can dump register directly?
>>
>>> +
>>> +		snprintf(prefix, sizeof(prefix), "q%d CQCFG: ", id);
>>> +		ufshcd_hex_dump(prefix,
>>> +			hba->mcq_base + MCQ_QCFG_SIZE * id +
>>> MCQ_QCFG_SQ_SIZE, MCQ_QCFG_CQ_SIZE);
>> Same to above comment.
>>> +
>>> +		for (i = 0; i < OPR_MAX ; i++) {
>>> +			snprintf(prefix, sizeof(prefix), "q%d OPR%d: ",
>>> id, i);
>>> +			ufshcd_hex_dump(prefix, mcq_opr_base(hba, i,
>>> id), mcq_opr_size[i]);
>> Same.
>>> +		}
>>> +	}
>>> +}
>>> +
>>>
>>>    
>>> @@ -574,7 +569,16 @@ void ufshcd_print_trs(struct ufs_hba *hba,
>>> unsigned long bitmap, bool pr_prdt)
>>>    		if (pr_prdt)
>>>    			ufshcd_hex_dump("UPIU PRDT: ", lrbp-
>>>> ucd_prdt_ptr,
>>>    				ufshcd_sg_entry_size(hba) *
>>> prdt_length);
>>> +
>>> +		if (is_mcq_enabled(hba)) {
>>> +			cmd = lrbp->cmd;
>>> +			if (!cmd)
>>> +				return;
>>> +			hwq = ufshcd_mcq_req_to_hwq(hba,
>>> scsi_cmd_to_rq(cmd));
>>> +			ufshcd_mcq_print_hwqs(hba, 1 << hwq->id);
>> Calling registers dump function in ufshcd_print_trs() is not
>> reasonable,
>> eg.. for each aborted request, it would print out all hwq registers,
>> it's not make sense.
>>
>> I think we should move it out of ufshcd_print_trs().
>>
>>> +		}
>>>    	}
>>> +
>>>    }
>>
>> Best Regards,
>>
>> Ziqi
>>