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From:   Michael Nazzareno Trimarchi <michael@amarulasolutions.com>
Date:   Mon, 27 Feb 2023 12:22:03 +0100
Message-ID: <CAOf5uwnuFBXF52Tbe7EFXcjzjbr-oOhn-fDVw=p8uZ8Y_Z7v+Q@mail.gmail.com>
Subject: Re: NXP imx6ull nonalignment buffer question
To:     Bough Chen <haibo.chen@nxp.com>
Cc:     Shawn Guo <shawnguo@kernel.org>,
        Fabio Estevam <festevam@gmail.com>,
        LKML <linux-kernel@vger.kernel.org>,
        linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
        "linux-mmc@vger.kernel.org" <linux-mmc@vger.kernel.org>,
        Ulf Hansson <ulf.hansson@linaro.org>
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Hi Bough

On Fri, Jan 13, 2023 at 8:19=E2=80=AFAM Michael Nazzareno Trimarchi
<michael@amarulasolutions.com> wrote:
>
> Hi
>
> On Fri, Jan 13, 2023 at 4:30 AM Bough Chen <haibo.chen@nxp.com> wrote:
> >
> > > -----Original Message-----
> > > From: Michael Nazzareno Trimarchi <michael@amarulasolutions.com>
> > > Sent: 2023=E5=B9=B41=E6=9C=889=E6=97=A5 21:02
> > > To: Bough Chen <haibo.chen@nxp.com>; Shawn Guo <shawnguo@kernel.org>;
> > > Fabio Estevam <festevam@gmail.com>; LKML <linux-kernel@vger.kernel.or=
g>
> > > Cc: linux-arm-kernel <linux-arm-kernel@lists.infradead.org>;
> > > linux-mmc@vger.kernel.org; Ulf Hansson <ulf.hansson@linaro.org>
> > > Subject: NXP imx6ull nonalignment buffer question
> > >
> > > Hi Haibo
> > >
> > > Working on imx6ulz design and found that if I send a sdio packet usin=
g the
> > > sdio_writesb the adma driver tries to handle it with two dma descript=
ors. The
> > > first one filled with the bytes up to 3 to cover the misalign and the=
n another
> > > buffer descriptor
> > >
> > >   offset =3D (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
> > >                          SDHCI_ADMA2_MASK;
> > >                 if (offset) {
> > >                         if (data->flags & MMC_DATA_WRITE) {
> > >                                 buffer =3D sdhci_kmap_atomic(sg);
> > >                                 memcpy(align, buffer, offset);
> > >                                 sdhci_kunmap_atomic(buffer);
> > >                         }
> > >
> > >                         /* tran, valid */
> > >                         __sdhci_adma_write_desc(host, &desc,
> > > align_addr,
> > >                                                 offset,
> > > ADMA2_TRAN_VALID);
> > >
> > >                         BUG_ON(offset > 65536);
> > >
> > >                         align +=3D SDHCI_ADMA2_ALIGN;
> > >                         align_addr +=3D SDHCI_ADMA2_ALIGN;
> > >
> > >                         addr +=3D offset;
> > >                         len -=3D offset;
> > >                 }
> > >
> > > In 48.7.4 Data Length Setting
> > > For either ADMA (ADMA1 or ADMA2) transfer, the data in the data buffe=
r must
> > > be word aligned, so the data length set in the descriptor must be a m=
ultiple of 4.
> > > I have noticed that this code does not work as expected.
> >
> > Hi Michael,
> >
> > My understanding is: for the sentence " the data in the data buffer mus=
t be word aligned", this means the start address of the data must be word a=
ligned, but not limit the data length.
> >
>
> Ok. My specific problem is that this seems not working on imx6ulz, I
> found the problem working on a wifi chipset, if the request gets split
> for no-alignment
> of the data in two dma descriptors, the chipset does not reply to me.
> Anyway, I will retest it with the upstream kernel again. I will check
> better and I will follow up if any more question
>

I have done some tests and I need this quirk
SDHCI_QUIRK_32BIT_ADMA_SIZE on imx6ulz cpu and I think that it applies
even on imx6ull.
Wifi can work only if the data on the sdio are aligned or we use
interrupt mode for no-alignment data. I did not find an errata and I
can not add as a quirk without a confirmation

Michael