Message-ID: <9866ba75-0b0c-e390-5962-c2d7ca2065fb@amd.com>
Date:   Mon, 27 Feb 2023 13:22:49 -0500
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Subject: Re: [PATCH v3 2/2] drm/amd: use fixed dsc bits-per-pixel from edid
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To:     Yaroslav Bolyukin <iam@lach.pw>, amd-gfx@lists.freedesktop.org,
        dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org
Cc:     Leo Li <sunpeng.li@amd.com>,
        Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>,
        Alex Deucher <alexander.deucher@amd.com>,
        =?UTF-8?Q?Christian_K=c3=b6nig?= <christian.koenig@amd.com>,
        "Pan, Xinhui" <Xinhui.Pan@amd.com>,
        David Airlie <airlied@gmail.com>,
        Daniel Vetter <daniel@ffwll.ch>,
        Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
        Maxime Ripard <mripard@kernel.org>,
        Thomas Zimmermann <tzimmermann@suse.de>,
        Jani Nikula <jani.nikula@intel.com>,
        Wayne Lin <Wayne.Lin@amd.com>
References: <20230226141051.21767-1-iam@lach.pw>
 <20230226141051.21767-3-iam@lach.pw>
From:   Harry Wentland <harry.wentland@amd.com>
In-Reply-To: <20230226141051.21767-3-iam@lach.pw>
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On 2/26/23 09:10, Yaroslav Bolyukin wrote:
> VESA vendor header from DisplayID spec may contain fixed bit per pixel
> rate, it should be respected by drm driver
> 

This will apply the fixed bpp for all modes. I don't think that's right.
It should apply only to VII timings.

Harry

> Signed-off-by: Yaroslav Bolyukin <iam@lach.pw>
> Reviewed-by: Wayne Lin <Wayne.Lin@amd.com>
> ---
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 ++
>  drivers/gpu/drm/amd/display/dc/core/dc_stream.c           | 2 ++
>  drivers/gpu/drm/amd/display/dc/dc_types.h                 | 3 +++
>  3 files changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> index 6fdc2027c2b4..dba720d5df4c 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> @@ -89,6 +89,8 @@ enum dc_edid_status dm_helpers_parse_edid_caps(
>  
>  	edid_caps->edid_hdmi = connector->display_info.is_hdmi;
>  
> +	edid_caps->dsc_fixed_bits_per_pixel_x16 = connector->display_info.dp_dsc_bpp;
> +
>  	sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads);
>  	if (sad_count <= 0)
>  		return result;
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
> index 72b261ad9587..a82362417379 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
> @@ -103,6 +103,8 @@ static bool dc_stream_construct(struct dc_stream_state *stream,
>  
>  	/* EDID CAP translation for HDMI 2.0 */
>  	stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble;
> +	stream->timing.dsc_fixed_bits_per_pixel_x16 =
> +		dc_sink_data->edid_caps.dsc_fixed_bits_per_pixel_x16;
>  
>  	memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg));
>  	stream->timing.dsc_cfg.num_slices_h = 0;
> diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
> index 27d0242d6cbd..22fedf4c7547 100644
> --- a/drivers/gpu/drm/amd/display/dc/dc_types.h
> +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
> @@ -228,6 +228,9 @@ struct dc_edid_caps {
>  	bool edid_hdmi;
>  	bool hdr_supported;
>  
> +	/* DisplayPort caps */
> +	uint32_t dsc_fixed_bits_per_pixel_x16;
> +
>  	struct dc_panel_patch panel_patch;
>  };
>