Date:   Tue, 28 Feb 2023 08:57:09 -0600
From:   Rob Herring <robh@kernel.org>
To:     Conor Dooley <conor@kernel.org>
Cc:     Evan Green <evan@rivosinc.com>,
        Palmer Dabbelt <palmer@rivosinc.com>, heiko@sntech.de,
        slewis@rivosinc.com, vineetg@rivosinc.com,
        Albert Ou <aou@eecs.berkeley.edu>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-riscv@lists.infradead.org
Subject: Re: [PATCH v3 4/7] dt-bindings: Add RISC-V misaligned access
 performance
Message-ID: <20230228145709.GA3198794-robh@kernel.org>
References: <20230221190858.3159617-1-evan@rivosinc.com>
 <20230221190858.3159617-5-evan@rivosinc.com>
 <Y/01c7sZ9ri5i8ao@spud>
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On Mon, Feb 27, 2023 at 10:57:55PM +0000, Conor Dooley wrote:
> Hey Evan,
> 
> On Tue, Feb 21, 2023 at 11:08:55AM -0800, Evan Green wrote:
> > From: Palmer Dabbelt <palmer@rivosinc.com>
> > 
> > This key allows device trees to specify the performance of misaligned
> > accesses to main memory regions from each CPU in the system.
> 
> Could you fold some of Palmer's explanation for why this must be in the
> devicetree? Think this is where he explained it:
> https://lore.kernel.org/all/mhng-8736b349-e27a-4372-81ca-3a25d2ec1e94@palmer-ri-x1c9/

I still don't think this belongs in DT and replied on the above thread.

Rob