Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3200C6FA8E for ; Tue, 28 Feb 2023 18:26:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229788AbjB1S0z (ORCPT ); Tue, 28 Feb 2023 13:26:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59726 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229755AbjB1S0x (ORCPT ); Tue, 28 Feb 2023 13:26:53 -0500 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C1F2E33479; Tue, 28 Feb 2023 10:26:24 -0800 (PST) Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 31S9gj3K028432; Tue, 28 Feb 2023 18:26:17 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=message-id : date : mime-version : subject : to : cc : references : from : in-reply-to : content-type : content-transfer-encoding; s=qcppdkim1; bh=5ra1VI/tE8mHc7byyB3aTDPoPxDKcCW+d2ksEpsuuZc=; b=TnqEJatyPL0oeYdwCrsaDw7AMHg4WP8kPinZzm7mkVE7Eau3YDWSVFZhRwLn2/RCm4B2 Tyu5DKT4M49lrd2D9r/FiFe9QGASmOygn//T2LPfEWLJEZTUBrcn+rH4/mILZmrsqxEu itk58D5XdpC9UYrxnEYTxVp+rF0KeDK/9toWz7xDRevn+fGdLb5DGRXvvmHsBbFcLRxQ CusNAcRUE0mWtX1vnec7h4miu+CePAShN8zdxMNy5UvZfQ87dhdyRJGD86+SsojR7GQ9 2Rqx6hvwfoErWLh++0Lq/gsGQi7TK/+4XBRXf5nSO3AueUnvGLBirlR+hikc6MezLJu6 TQ== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3p1f7n1kmv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 28 Feb 2023 18:26:16 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 31SIQEHY012714 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 28 Feb 2023 18:26:14 GMT Received: from [10.110.126.127] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Tue, 28 Feb 2023 10:26:13 -0800 Message-ID: <530d2b86-1889-388d-4279-7ddc1ad9dfbb@quicinc.com> Date: Tue, 28 Feb 2023 10:26:12 -0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.6.2 Subject: Re: [PATCH v2] drm/msm/disp/dpu: fix sc7280_pp base offset Content-Language: en-US To: Kuogee Hsieh , , , , , , , , , , CC: , , , , References: <1677533800-3125-1-git-send-email-quic_khsieh@quicinc.com> From: Abhinav Kumar In-Reply-To: <1677533800-3125-1-git-send-email-quic_khsieh@quicinc.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 45Tn4hqAKRknOKOobcVPZBf2jlPahZaU X-Proofpoint-ORIG-GUID: 45Tn4hqAKRknOKOobcVPZBf2jlPahZaU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-02-28_15,2023-02-28_03,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 phishscore=0 lowpriorityscore=0 malwarescore=0 mlxlogscore=999 clxscore=1015 mlxscore=0 adultscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2302280153 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2/27/2023 1:36 PM, Kuogee Hsieh wrote: > At sc7280, pingpong block is used to management the dither effects > to reduce distortion at panel. Currently pingpong-0 base offset is > wrongly set at 0x59000. This mistake will not cause system to crash. > However it will make dither not work. This patch correct sc7280 ping > pong-0 block base offset. > > Changes in v2: > -- add more details info n regrading of pingpong block at commit text > > Fixes: 591e34a091d1 ("drm/msm/disp/dpu1: add support for display for SC7280 target") > Signed-off-by: Kuogee Hsieh Reviewed-by: Abhinav Kumar > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > index 7deffc9f9..286437e 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > @@ -1707,7 +1707,7 @@ static const struct dpu_pingpong_cfg sm8350_pp[] = { > }; > > static const struct dpu_pingpong_cfg sc7280_pp[] = { > - PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1), > + PP_BLK("pingpong_0", PINGPONG_0, 0x69000, 0, sc7280_pp_sblk, -1, -1), > PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1), > PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1), > PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),