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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT058.mail.protection.outlook.com (10.13.177.58) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6156.12 via Frontend Transport; Wed, 1 Mar 2023 15:08:43 +0000 Received: from AUS-LX-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Wed, 1 Mar 2023 09:08:42 -0600 From: Mario Limonciello To: Shyam Sundar S K CC: Mario Limonciello , Hans de Goede , Mark Gross , , Subject: [PATCH 1/2] platform/x86/amd: pmc: Add a helper for checking minimum SMU version Date: Wed, 1 Mar 2023 09:08:19 -0600 Message-ID: <20230301150821.9791-1-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT058:EE_|SJ2PR12MB7917:EE_ X-MS-Office365-Filtering-Correlation-Id: c0f717cc-e8fd-4a06-c4d3-08db1a66d941 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Mar 2023 15:08:43.6540 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c0f717cc-e8fd-4a06-c4d3-08db1a66d941 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT058.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB7917 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In a few locations there is some boilerplate code for checking minimum SMU version. Switch this to a helper for this check. No intended functional changes. Signed-off-by: Mario Limonciello --- drivers/platform/x86/amd/pmc.c | 49 +++++++++++++++++----------------- 1 file changed, 24 insertions(+), 25 deletions(-) diff --git a/drivers/platform/x86/amd/pmc.c b/drivers/platform/x86/amd/pmc.c index 2edaae04a691..c42fa47381c3 100644 --- a/drivers/platform/x86/amd/pmc.c +++ b/drivers/platform/x86/amd/pmc.c @@ -418,6 +418,22 @@ static int amd_pmc_get_smu_version(struct amd_pmc_dev *dev) return 0; } +static bool amd_pmc_verify_min_version(struct amd_pmc_dev *pdev, int major, int minor) +{ + if (!pdev->major) { + int rc = amd_pmc_get_smu_version(pdev); + + if (rc) { + dev_warn(pdev->dev, "failed to read SMU version: %d\n", rc); + return false; + } + } + if (pdev->major > major) + return true; + + return pdev->major == major && pdev->minor >= minor; +} + static ssize_t smu_fw_version_show(struct device *d, struct device_attribute *attr, char *buf) { @@ -526,14 +542,7 @@ static int amd_pmc_idlemask_show(struct seq_file *s, void *unused) struct amd_pmc_dev *dev = s->private; int rc; - /* we haven't yet read SMU version */ - if (!dev->major) { - rc = amd_pmc_get_smu_version(dev); - if (rc) - return rc; - } - - if (dev->major > 56 || (dev->major >= 55 && dev->minor >= 37)) { + if (amd_pmc_verify_min_version(dev, 55, 37)) { rc = amd_pmc_idlemask_read(dev, NULL, s); if (rc) return rc; @@ -686,15 +695,8 @@ static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev) static int amd_pmc_czn_wa_irq1(struct amd_pmc_dev *pdev) { struct device *d; - int rc; - if (!pdev->major) { - rc = amd_pmc_get_smu_version(pdev); - if (rc) - return rc; - } - - if (pdev->major > 64 || (pdev->major == 64 && pdev->minor > 65)) + if (amd_pmc_verify_min_version(pdev, 64, 66)) return 0; d = bus_find_device_by_name(&serio_bus, NULL, "serio0"); @@ -718,14 +720,10 @@ static int amd_pmc_verify_czn_rtc(struct amd_pmc_dev *pdev, u32 *arg) struct rtc_time tm; int rc; - /* we haven't yet read SMU version */ - if (!pdev->major) { - rc = amd_pmc_get_smu_version(pdev); - if (rc) - return rc; - } + if (disable_workarounds) + return 0; - if (pdev->major < 64 || (pdev->major == 64 && pdev->minor < 53)) + if (!amd_pmc_verify_min_version(pdev, 64, 53)) return 0; rtc_device = rtc_class_open("rtc0"); @@ -772,13 +770,14 @@ static void amd_pmc_s2idle_prepare(void) /* Reset and Start SMU logging - to monitor the s0i3 stats */ amd_pmc_setup_smu_logging(pdev); - /* Activate CZN specific platform bug workarounds */ - if (pdev->cpu_id == AMD_CPU_ID_CZN && !disable_workarounds) { + switch (pdev->cpu_id) { + case AMD_CPU_ID_CZN: rc = amd_pmc_verify_czn_rtc(pdev, &arg); if (rc) { dev_err(pdev->dev, "failed to set RTC: %d\n", rc); return; } + break; } msg = amd_pmc_get_os_hint(pdev); -- 2.34.1