Date:   Wed, 01 Mar 2023 09:16:54 -0800
From:   "H. Peter Anvin" <hpa@zytor.com>
To:     "Maciej W. Rozycki" <macro@orcam.me.uk>,
        Bjorn Helgaas <bhelgaas@google.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>
CC:     x86@kernel.org, linux-pci@vger.kernel.org,
        linux-kernel@vger.kernel.org
Subject: =?US-ASCII?Q?Re=3A_=5BPING=5E3=5D=5BRESEND=5E3=5D=5BPAT?= =?US-ASCII?Q?CH_v3=5D_x86/PCI=3A_Add_support?= =?US-ASCII?Q?_for_the_Intel_82378ZB/82379AB_=28SIO/SIO=2EA=29_PIRQ_router?=
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References: <alpine.DEB.2.21.2301081956290.65308@angie.orcam.me.uk> <alpine.DEB.2.21.2303011311540.57556@angie.orcam.me.uk>
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On March 1, 2023 5:14:59 AM PST, "Maciej W=2E Rozycki" <macro@orcam=2Eme=2E=
uk> wrote:
>On Sun, 8 Jan 2023, Maciej W=2E Rozycki wrote:
>
>> The Intel 82378ZB System I/O (SIO) and 82379AB System I/O APIC (SIO=2EA=
)=20
>> ISA bridges implement PCI interrupt steering with a PIRQ router[1][2]=
=20
>> that is exactly the same as that of the PIIX and ICH southbridges (or=
=20
>> actually the other way round, given that the SIO ASIC was there first)=
=2E
>
> Ping for:
><https://lore=2Ekernel=2Eorg/lkml/alpine=2EDEB=2E2=2E21=2E2301081956290=
=2E65308@angie=2Eorcam=2Eme=2Euk/>=2E
>
> I think the patch is fairly obvious=2E  Are there any outstanding concer=
ns=20
>that prevent it from being applied?
>
>  Maciej
>

Has this patch been actually tested on a real machine, or is it purely the=
oretical?