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From:   Tim Harvey <tharvey@gateworks.com>
Date:   Wed, 1 Mar 2023 09:29:16 -0800
Message-ID: <CAJ+vNU1bBLnJ2_mLmdW-JSysK1YDXsdS01SEB9+BUNytNGMhOA@mail.gmail.com>
Subject: Re: [RFC PATCH] irqchip/gic-v3: Claim iomem resources
To:     Robin Murphy <robin.murphy@arm.com>, Marc Zyngier <maz@kernel.org>
Cc:     Ulf Hansson <ulf.hansson@linaro.org>,
        Al Cooper <alcooperx@gmail.com>,
        Adrian Hunter <adrian.hunter@intel.com>, tglx@linutronix.de,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
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On Wed, Mar 1, 2023 at 8:13=E2=80=AFAM Robin Murphy <robin.murphy@arm.com> =
wrote:
>
> On 2023-02-28 23:22, Marc Zyngier wrote:
> > On Tue, 28 Feb 2023 23:11:15 +0000,
> > Tim Harvey <tharvey@gateworks.com> wrote:
> >>
> >> I have bisected a kernel issue where octeontx (CN803x) will hang on
> >> reboot caused by commit c0db06fd0993 ("mmc: core: Disable card detect
> >> during shutdown"). This commit made it into 5.16 and stable kernels.
> >> I've found that the patch here which is commit 2b2cd74a06c3 resolves
> >> this hang but I'm not entirely clear why.
> >>
> >> Does anyone have a good explanation of why the hang occurs in the
> >> first place and why this resolves it? I would like to get the proper
> >> fix into the affected stable branches.
> >
> > Wild guess: the reservation prevents some other driver from probing
> > because the firmware describes overlapping ranges, and that driver is
> > what is causing your above hang.
>
> Indeed, according to [1], the GIC appears to overlap one of the "PCIe"
> windows of &ecam0, which conveniently appears to be the parent of the
> MMC controller as well.
>
> Robin.
>
> [1]
> https://github.com/Gateworks/dts-newport/blob/sdk-10.1.1.0-newport/cn81xx=
-linux.dtsi

Robin and Marc,

Thanks! Yes, this patch exposes an issue in my dt which ends up
killing off ecam0 thus hiding the original 'hang on reboot' issue I
was trying to find related to mmc with a quick bisect.

As you expected ecam0 fails probe:
[    0.977514] pci-host-generic: probe of 848000000000.pci failed with erro=
r -12

Cavium/Marvell never mainlined their cn81xx device-tree and their
latest SDK appears to still have this issue. It looks to me like the
first mem range in ecam0 is just wrong and needs to be removed:
@@ -226,8 +226,7 @@ ecam0: pci@848000000000 {
                        u-boot,dm-pre-reloc;
                        dma-coherent;
                        reg =3D <0x8480 0x00000000 0 0x02000000>;  /*
Configuration space
 */
-                       ranges =3D <0x03000000 0x8010 0x00000000 0x8010
0x00000000 0x080
0x00000000>, /* mem ranges */
-                                <0x03000000 0x8100 0x00000000 0x8100
0x00000000 0x80
0x00000000>, /* SATA */
+                       ranges =3D <0x03000000 0x8100 0x00000000 0x8100
0x00000000 0x80
0x00000000>, /* SATA */
                                 <0x03000000 0x8680 0x00000000 0x8680
0x00000000 0x160
0x28000000>, /* UARTs */
                                 <0x03000000 0x87e0 0x2c000000 0x87e0
0x2c000000 0x000
0x94000000>, /* PEMs */
                                 <0x03000000 0x8400 0x00000000 0x8400
0x00000000 0x010
0x00000000>, /* RNM */

This results in:
[    0.911162] pci-host-generic 848000000000.pci: host bridge
/soc@0/pci@848000000000 ranges:
[    0.919506] pci-host-generic 848000000000.pci:      MEM
0x810000000000..0x817fffffffff -> 0x810000000000
[    0.929018] pci-host-generic 848000000000.pci:      MEM
0x868000000000..0x87e027ffffff -> 0x868000000000
[    0.938531] pci-host-generic 848000000000.pci:      MEM
0x87e02c000000..0x87e0bfffffff -> 0x87e02c000000
[    0.948039] pci-host-generic 848000000000.pci:      MEM
0x840000000000..0x840fffffffff -> 0x840000000000
[    0.957543] pci-host-generic 848000000000.pci:      MEM
0x843000000000..0x8431ffffffff -> 0x843000000000
[    0.967054] pci-host-generic 848000000000.pci:      MEM
0x87e0c6000000..0x87ffffffffff -> 0x87e0c6000000
[    0.976562] pci-host-generic 848000000000.pci: Memory resource size
exceeds max for 32 bits
[    0.984923] pci-host-generic 848000000000.pci: Memory resource size
exceeds max for 32 bits
[    0.993284] pci-host-generic 848000000000.pci: Memory resource size
exceeds max for 32 bits
[    1.001645] pci-host-generic 848000000000.pci: Memory resource size
exceeds max for 32 bits
[    1.010008] pci-host-generic 848000000000.pci: Memory resource size
exceeds max for 32 bits
[    1.018404] pci-host-generic 848000000000.pci: ECAM at [mem
0x848000000000-0x848001ffffff] for [bus 00-1f]
[    1.028240] pci-host-generic 848000000000.pci: PCI host bridge to bus 00=
00:00
[    1.035412] pci_bus 0000:00: root bus resource [bus 00-1f]
[    1.040907] pci_bus 0000:00: root bus resource [mem
0x810000000000-0x817fffffffff]
[    1.048488] pci_bus 0000:00: root bus resource [mem
0x868000000000-0x87e027ffffff]
[    1.056070] pci_bus 0000:00: root bus resource [mem
0x87e02c000000-0x87e0bfffffff]
[    1.063652] pci_bus 0000:00: root bus resource [mem
0x840000000000-0x840fffffffff]
[    1.071232] pci_bus 0000:00: root bus resource [mem
0x843000000000-0x8431ffffffff]
[    1.078815] pci_bus 0000:00: root bus resource [mem
0x87e0c6000000-0x87ffffffffff]

and all of the PCI devices appear to work fine. Is there an additional
issue I need to work on regarding the 'Memory resource size exceeds
max for 32 bits' warning above?

Best Regards,

Tim