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[83.9.32.99]) by smtp.gmail.com with ESMTPSA id q20-20020ac24a74000000b004d5a6dcb94fsm2097650lfp.33.2023.03.02.03.10.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 02 Mar 2023 03:10:07 -0800 (PST) Message-ID: <5f23ddc7-1bbf-320b-cb5a-9b1bfde3dfff@linaro.org> Date: Thu, 2 Mar 2023 12:10:05 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH 05/18] media: venus: hfi_venus: Sanitize venus_boot_core() per-VPU-version To: Dikshita Agarwal , Stanimir Varbanov , Vikash Garodia , Andy Gross , Bjorn Andersson , Mauro Carvalho Chehab , Dikshita Agarwal , Bryan O'Donoghue , Dikshita Agarwal , Mansur Alisha Shaik , Jonathan Marek Cc: Mauro Carvalho Chehab , Stanimir Varbanov , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Vikash Garodia References: <20230228-topic-venus-v1-0-58c2c88384e9@linaro.org> <20230228-topic-venus-v1-5-58c2c88384e9@linaro.org> <769b4971-aed8-ce6a-b77a-29660957ec38@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <769b4971-aed8-ce6a-b77a-29660957ec38@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2.03.2023 12:00, Dikshita Agarwal wrote: > > On 2/28/2023 8:54 PM, Konrad Dybcio wrote: >> The current assumption of IS_V6 is overgeneralized. Adjust the logic >> to take the VPU hardware version into account. >> >> Signed-off-by: Konrad Dybcio >> --- >>   drivers/media/platform/qcom/venus/hfi_venus.c | 10 ++++++---- >>   1 file changed, 6 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/media/platform/qcom/venus/hfi_venus.c b/drivers/media/platform/qcom/venus/hfi_venus.c >> index 4ccf31147c2a..772e5e9cf127 100644 >> --- a/drivers/media/platform/qcom/venus/hfi_venus.c >> +++ b/drivers/media/platform/qcom/venus/hfi_venus.c >> @@ -448,20 +448,21 @@ static int venus_boot_core(struct venus_hfi_device *hdev) >>   { >>       struct device *dev = hdev->core->dev; >>       static const unsigned int max_tries = 100; >> -    u32 ctrl_status = 0, mask_val; >> +    u32 ctrl_status = 0, mask_val = 0; >>       unsigned int count = 0; >>       void __iomem *cpu_cs_base = hdev->core->cpu_cs_base; >>       void __iomem *wrapper_base = hdev->core->wrapper_base; >>       int ret = 0; >>         writel(BIT(VIDC_CTRL_INIT_CTRL_SHIFT), cpu_cs_base + VIDC_CTRL_INIT); >> -    if (IS_V6(hdev->core)) { >> +    if (IS_IRIS1(hdev->core) || IS_IRIS2(hdev->core) || IS_IRIS2_1(hdev->core)) { > > I think the IRIS1 check can be removed from here as we are not handling IRIS1 related things at other places. > > we can add the required checks for IRIS1 when we add support for any IRIS1 based chipset. Up to you really, I plan on getting IRIS1 (SM8150) supported and have some mumbling going on for that on my local branch. FWIW these checks are logically correct and I would personally prefer not to have to go through each one of them and remove them just to bring them back soon. Konrad > > Thanks, > > Dikshita > >>           mask_val = readl(wrapper_base + WRAPPER_INTR_MASK); >>           mask_val &= ~(WRAPPER_INTR_MASK_A2HWD_BASK_V6 | >>                     WRAPPER_INTR_MASK_A2HCPU_MASK); >>       } else { >>           mask_val = WRAPPER_INTR_MASK_A2HVCODEC_MASK; >>       } >> + >>       writel(mask_val, wrapper_base + WRAPPER_INTR_MASK); >>       writel(1, cpu_cs_base + CPU_CS_SCIACMDARG3); >>   @@ -480,10 +481,11 @@ static int venus_boot_core(struct venus_hfi_device *hdev) >>       if (count >= max_tries) >>           ret = -ETIMEDOUT; >>   -    if (IS_V6(hdev->core)) { >> +    if (IS_AR50_LITE(hdev->core) || IS_IRIS2(hdev->core) || IS_IRIS2_1(hdev->core)) >>           writel(0x1, cpu_cs_base + CPU_CS_H2XSOFTINTEN_V6); >> + >> +    if (IS_IRIS2(hdev->core) || IS_IRIS2_1(hdev->core)) >>           writel(0x0, cpu_cs_base + CPU_CS_X2RPMH_V6); >> -    } >>         return ret; >>   } >>