Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66266C6FA8E for ; Thu, 2 Mar 2023 11:13:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230202AbjCBLN4 (ORCPT ); Thu, 2 Mar 2023 06:13:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34128 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230281AbjCBLNZ (ORCPT ); Thu, 2 Mar 2023 06:13:25 -0500 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E8C6D474DB for ; Thu, 2 Mar 2023 03:12:39 -0800 (PST) Received: by mail-wr1-x42b.google.com with SMTP id g3so7259962wri.6 for ; Thu, 02 Mar 2023 03:12:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bytedance.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=W52wEjM0mHEImMyCikVowjMrBLWr/NXovNQ5aX5mqUY=; b=UuDoUEMbv5C/Rt71oIZYY+UFys53GNRZFiZCWwLzPSehXmE2ry44f1Ij/tq5BRMOKr 63qepzGOdbmXGxkuHwXQ+/84oZTG1qlm2hmcUvyAvparLsspHrJ08inWrNznQ2hy7Alb cT7cQ8CNNutknMb+PJZFKQ+htxvbCQg19R/QKyscVkg1qi5sb6fZvgnHI6V5C1PSwWma 0WnSiPt0icHQ0icz9nrppViWa94JYB39504FsPBw0zZMEK19cBYVDq6ruO9P4xm3xEMc XQbN5HDut56dtkXuDj+uqpuCnJEZ4M+unoB1liq9ypwSH7qTpheSfHU5XzoTC3m2eDnU k1mA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=W52wEjM0mHEImMyCikVowjMrBLWr/NXovNQ5aX5mqUY=; b=ZvKzWP2qLlVSWOv019EdweUlMD+AWQJLMydfXs9zXbNC8nS4hQzuHi9lOT+EAdqkIe 5p+bxQqg1m3taBVT3AYxcFVoPc8pYWgEWzV2Jh0Qt/r3v5mlWjxnD6DmiPBDVvnf68Gx 3c+EWKSCHys54Dnpi6UGBHKNAajaFOLnCgiuzqHFPYUuknSKu+CZSTd5MzfMYyB9tCUY vDXae5TylEnHI3l5c8/Jto3Vso1mUqQS1h0+gwMPLDf5VbRGA5ae2/ulUy0y9aPG+nRo 2qby4oilPmk7xLJD1Qy8JQZcQel/jxnzg1wGI1DR9zlc8fF1fRcFiUweRz6DBqD5mmYn JAeA== X-Gm-Message-State: AO0yUKUmNQKWYmv62tmz+wX52/atq0j7w7aQxKFBRqKkvBs1RqZo9+iR ibf9O2ekJ6h6jYYgzkNY/8AUxg== X-Google-Smtp-Source: AK7set9zkyJBDHhyR5g5CmVYoTxvTrStQPl+SxB68YPWsjw/pSJ9UScCnssrt/YxdzQjmtTqzPBQyQ== X-Received: by 2002:adf:fa0d:0:b0:2c7:be1:467b with SMTP id m13-20020adffa0d000000b002c70be1467bmr6839166wrr.31.1677755558441; Thu, 02 Mar 2023 03:12:38 -0800 (PST) Received: from usaari01.cust.communityfibre.co.uk ([2a02:6b6a:b566:0:11aa:3c13:d3e:eb29]) by smtp.gmail.com with ESMTPSA id a5-20020a5d4565000000b002c3f81c51b6sm14724830wrc.90.2023.03.02.03.12.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Mar 2023 03:12:37 -0800 (PST) From: Usama Arif To: dwmw2@infradead.org, tglx@linutronix.de, kim.phillips@amd.com, brgerst@gmail.com Cc: piotrgorski@cachyos.org, oleksandr@natalenko.name, arjan@linux.intel.com, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, x86@kernel.org, pbonzini@redhat.com, paulmck@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, rcu@vger.kernel.org, mimoja@mimoja.de, hewenliang4@huawei.com, thomas.lendacky@amd.com, seanjc@google.com, pmenzel@molgen.mpg.de, fam.zheng@bytedance.com, punit.agrawal@bytedance.com, simon.evans@bytedance.com, liangma@liangbit.com, David Woodhouse , Usama Arif , "Guilherme G . Piccoli" Subject: [PATCH v13 08/11] x86/smpboot: Remove initial_gs Date: Thu, 2 Mar 2023 11:12:24 +0000 Message-Id: <20230302111227.2102545-9-usama.arif@bytedance.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230302111227.2102545-1-usama.arif@bytedance.com> References: <20230302111227.2102545-1-usama.arif@bytedance.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Brian Gerst Given its CPU#, each CPU can find its own per-cpu offset, and directly set GSBASE accordingly. The global variable can be eliminated. Signed-off-by: Brian Gerst Reviewed-by: David Woodhouse Signed-off-by: David Woodhouse Tested-by: Usama Arif Signed-off-by: Usama Arif Tested-by: Guilherme G. Piccoli --- arch/x86/include/asm/realmode.h | 1 - arch/x86/kernel/acpi/sleep.c | 1 - arch/x86/kernel/head_64.S | 22 ++++++++-------------- arch/x86/kernel/smpboot.c | 2 -- 4 files changed, 8 insertions(+), 18 deletions(-) diff --git a/arch/x86/include/asm/realmode.h b/arch/x86/include/asm/realmode.h index a336feef0af1..f6a1737c77be 100644 --- a/arch/x86/include/asm/realmode.h +++ b/arch/x86/include/asm/realmode.h @@ -59,7 +59,6 @@ extern struct real_mode_header *real_mode_header; extern unsigned char real_mode_blob_end[]; extern unsigned long initial_code; -extern unsigned long initial_gs; extern unsigned long initial_stack; #ifdef CONFIG_AMD_MEM_ENCRYPT extern unsigned long initial_vc_handler; diff --git a/arch/x86/kernel/acpi/sleep.c b/arch/x86/kernel/acpi/sleep.c index de89bb4719d0..1328c221af30 100644 --- a/arch/x86/kernel/acpi/sleep.c +++ b/arch/x86/kernel/acpi/sleep.c @@ -127,7 +127,6 @@ int x86_acpi_suspend_lowlevel(void) * value is in the actual %rsp register. */ current->thread.sp = (unsigned long)temp_stack + sizeof(temp_stack); - initial_gs = per_cpu_offset(smp_processor_id()); smpboot_control = smp_processor_id(); #endif initial_code = (unsigned long)wakeup_long64; diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index a5b46c2fba05..6a8238702eab 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -66,18 +66,10 @@ SYM_CODE_START_NOALIGN(startup_64) leaq _text(%rip), %rdi - /* - * initial_gs points to initial fixed_percpu_data struct with storage for - * the stack protector canary. Global pointer fixups are needed at this - * stage, so apply them as is done in fixup_pointer(), and initialize %gs - * such that the canary can be accessed at %gs:40 for subsequent C calls. - */ + /* Setup GSBASE to allow stack canary access for C code */ movl $MSR_GS_BASE, %ecx - movq initial_gs(%rip), %rax - movq $_text, %rdx - subq %rdx, %rax - addq %rdi, %rax - movq %rax, %rdx + leaq INIT_PER_CPU_VAR(fixed_percpu_data)(%rip), %rdx + movl %edx, %eax shrq $32, %rdx wrmsr @@ -294,8 +286,11 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL) * the per cpu areas are set up. */ movl $MSR_GS_BASE,%ecx - movl initial_gs(%rip),%eax - movl initial_gs+4(%rip),%edx +#ifndef CONFIG_SMP + leaq INIT_PER_CPU_VAR(fixed_percpu_data)(%rip), %rdx +#endif + movl %edx, %eax + shrq $32, %rdx wrmsr /* Setup and Load IDT */ @@ -437,7 +432,6 @@ SYM_CODE_END(vc_boot_ghcb) __REFDATA .balign 8 SYM_DATA(initial_code, .quad x86_64_start_kernel) -SYM_DATA(initial_gs, .quad INIT_PER_CPU_VAR(fixed_percpu_data)) #ifdef CONFIG_AMD_MEM_ENCRYPT SYM_DATA(initial_vc_handler, .quad handle_vc_boot_ghcb) #endif diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index a22460a07cf8..b04520085582 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -1084,8 +1084,6 @@ int common_cpu_up(unsigned int cpu, struct task_struct *idle) #ifdef CONFIG_X86_32 /* Stack for startup_32 can be just as for start_secondary onwards */ per_cpu(pcpu_hot.top_of_stack, cpu) = task_top_of_stack(idle); -#else - initial_gs = per_cpu_offset(cpu); #endif return 0; } -- 2.25.1