Message-ID: <3b6f866b-1d38-2605-df35-7a937e73a2fe@linaro.org>
Date:   Thu, 2 Mar 2023 17:16:50 +0100
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Reply-To: neil.armstrong@linaro.org
Subject: Re: [PATCH] arm64: dts: qcom: sm8550: fix LPASS pinctrl slew base
 address
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To:     Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        Andy Gross <agross@kernel.org>,
        Bjorn Andersson <andersson@kernel.org>,
        Konrad Dybcio <konrad.dybcio@linaro.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org
References: <20230302154724.856062-1-krzysztof.kozlowski@linaro.org>
From:   Neil Armstrong <neil.armstrong@linaro.org>
Organization: Linaro Developer Services
In-Reply-To: <20230302154724.856062-1-krzysztof.kozlowski@linaro.org>
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Precedence: bulk

On 02/03/2023 16:47, Krzysztof Kozlowski wrote:
> The second LPASS pin controller IO address is supposed to be the MCC
> range which contains the slew rate registers.  The Linux driver then
> accesses slew rate register with hard-coded offset (0xa000).  However
> the DTS contained the address of slew rate register as the second IO
> address, thus any reads were effectively pass the memory space and lead
> to "Internal error: synchronous external aborts" when applying pin
> configuration.
> 
> Fixes: 6de7f9c34358 ("arm64: dts: qcom: sm8550: add GPR and LPASS pin controller")
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> 
> ---
> 
> Fix for current cycle - v6.3-rc1.
> ---
>   arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index 1dea055a6815..6296eb7adecd 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -2001,7 +2001,7 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
>   		lpass_tlmm: pinctrl@6e80000 {
>   			compatible = "qcom,sm8550-lpass-lpi-pinctrl";
>   			reg = <0 0x06e80000 0 0x20000>,
> -			      <0 0x0725a000 0 0x10000>;
> +			      <0 0x07250000 0 0x10000>;
>   			gpio-controller;
>   			#gpio-cells = <2>;
>   			gpio-ranges = <&lpass_tlmm 0 0 23>;

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>