Date:   Fri, 3 Mar 2023 09:15:45 -0400
From:   Jason Gunthorpe <jgg@nvidia.com>
To:     Baolu Lu <baolu.lu@linux.intel.com>
Cc:     Jean-Philippe Brucker <jean-philippe@linaro.org>,
        Jacob Pan <jacob.jun.pan@linux.intel.com>,
        LKML <linux-kernel@vger.kernel.org>, iommu@lists.linux.dev,
        Joerg Roedel <joro@8bytes.org>,
        Jean-Philippe Brucker <jean-philippe@linaro.com>,
        Dave Hansen <dave.hansen@intel.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        X86 Kernel <x86@kernel.org>, bp@alien8.de,
        "H. Peter Anvin" <hpa@zytor.com>,
        Peter Zijlstra <peterz@infradead.org>, corbet@lwn.net,
        vkoul@kernel.org, dmaengine@vger.kernel.org,
        linux-doc@vger.kernel.org, Robin Murphy <robin.murphy@arm.com>,
        Will Deacon <will@kernel.org>,
        David Woodhouse <dwmw2@infradead.org>,
        Raj Ashok <ashok.raj@intel.com>,
        "Tian, Kevin" <kevin.tian@intel.com>, Yi Liu <yi.l.liu@intel.com>,
        "Yu, Fenghua" <fenghua.yu@intel.com>,
        Dave Jiang <dave.jiang@intel.com>,
        Kirill Shutemov <kirill.shutemov@linux.intel.com>
Subject: Re: [PATCH v4 3/6] iommu/sva: Stop using ioasid_set for SVA
Message-ID: <ZAHzAa0mnilf0N9K@nvidia.com>
References: <20230301235646.2692846-1-jacob.jun.pan@linux.intel.com>
 <20230301235646.2692846-4-jacob.jun.pan@linux.intel.com>
 <3b7fb4d3-1fe9-a3be-46ad-c271be9f96c7@linux.intel.com>
 <20230302091707.58d59964@jacob-builder>
 <794c7dad-2e62-3afa-ea10-92179b0d1659@linux.intel.com>
 <20230303093235.GB361458@myrica>
 <3b2c6fe9-821f-9b84-acb6-777e8517a0fc@linux.intel.com>
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <3b2c6fe9-821f-9b84-acb6-777e8517a0fc@linux.intel.com>
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?QWHLMy5pDCxZze794/mGncM7mipI36BPmVbAQSOhEtzV69iOLrs4M/e+Yl4G?=
 =?us-ascii?Q?BcvgeaiQbG6ZKjVCSwzfaumkBA9/x+Y43x+vC9X1p36U7yXTO8EAPD2RPN8w?=
 =?us-ascii?Q?s92VP/FgKZoH9QCGof9sNF3zjrZmAZ7n/FK93W9Ki3CmOXq9VsjfdjCr3B6T?=
 =?us-ascii?Q?RTJSt3KIWstXq4UmE47IFiummNxAZJzhSTpXmDAYZ4o0sWJtasrChfoNqa9s?=
 =?us-ascii?Q?Be+/7UNv03/PiO7i/y2d7sVVXaLm7jXYCj04FxU8r9LQQZnrBE5gM7wXC/rS?=
 =?us-ascii?Q?0iEeQCCXicVw68xeSApR6dKzZ7X/Z9liFFiYAPTKWjJ7RxJdAe/tHtZnyGgw?=
 =?us-ascii?Q?J3V8aeI8rCx9zqUx1wjTt8ZYrulBRycJZ/ZUrD5Wv0iO6DuT0Q5ZIbqBFpIY?=
 =?us-ascii?Q?muW7nBcHnRRschoTcI65+0FryQbvdkx68b0zKKOWXibU+BwHwlj5sOEUKqHp?=
 =?us-ascii?Q?uM9VB25x2UabWeZ7IAXVuxv/5wKsdKLfPXd0ddjG2tpsiEpE+603E+3b3RGL?=
 =?us-ascii?Q?SyFrKIrtNG65+NzBk61Ymk7eytpQIYuoEQFCYnf9sjZ10hd161M+1hjJSxTi?=
 =?us-ascii?Q?5UsslMIKNpMqgyR8j6o1ziRFrbbeU4xeOTN+bGr79ZXe+IWL7BqV/S5Jn/HE?=
 =?us-ascii?Q?+8gH0crOtvR92/koLMJWGEw4MknxFtZwc5FcgsbJS7i0cWHsPtdIQxWRZ+0f?=
 =?us-ascii?Q?PXpFd5kzvtCFslgphtEGyU665qnUfvw7UFAZOVqcqsv6MGezcBXo3dmg8LWe?=
 =?us-ascii?Q?A76KyU1KyBSZt5VCZ2xHZuSoKA7WwfRyK4VWQ6DJf4IExOAVeAZ2Mzyi0HYl?=
 =?us-ascii?Q?oh0FrsQBA1iUsvysdL5XCYxTDuQrJvu+gIVMk2jtgrUcgW+nK4TLfhKwnjjE?=
 =?us-ascii?Q?os+oIWEl/lpd22gMJmUpfi4ZeJlfJU/Z0jpifaojuUjimQREjxZhi+PrsMds?=
 =?us-ascii?Q?AXaC0vr0I5VHysSwGwilwl9JDz7zY/1kZskqi5lW+N23OvoxX+mtejUQVl4p?=
 =?us-ascii?Q?irLFkCRWZUrM62YobCUSfKTXjZNGO3jRk8z4dznTqTQBga/aEPfb2+RFFGfW?=
 =?us-ascii?Q?PrlcrNuRextKnoma2Zyr5bsMzr0DsfPe1Dw5VGclnIYDlj4uZT45QfRXXZGG?=
 =?us-ascii?Q?nL7D5h2cvQCzZyPdj/zwNnW/imFxMLHdg3hB4qZ7gyRsw6/CTsXGZP6oQysN?=
 =?us-ascii?Q?MyTxI5UBmbHO+NGTkrBdEzTSyVeIhnl/Hjo5ep694dDJyktVdJk1/5zu9I6W?=
 =?us-ascii?Q?hPUTBMTcF8dQU+Q8EFsxFDL4mb7mA643XE+rh6VLNRr86tgO4ELobMa0HZdk?=
 =?us-ascii?Q?KyhZfvlwI12pxJoz7vCOkNrbF4jqKC2l9Nif65hfN1JFUeMXJXM5FR7dOqjz?=
 =?us-ascii?Q?02rE7jvZargbCKjp0/LXLhQyxduum7sKquQDeKT8L5z0o3CZSrrgW/3+o6TC?=
 =?us-ascii?Q?WozNGaEG9AlBYOVpdeNvMS9mm2IKQ7ccAppCAcZE8prxZ3kaTaEkpd3oO0/r?=
 =?us-ascii?Q?HlY8y5oo6o3ejYMJDImu1cMucfexnXQy0eWxQfz/GKgHmSgLAF7qYa3tsbja?=
 =?us-ascii?Q?QNglCGIkjQ6WZ9/0hvfpEgM2oCqjAMXegRMcp2ho?=
X-OriginatorOrg: Nvidia.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 37933b1c-09cf-46a2-3c02-08db1be96785
X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Mar 2023 13:15:48.3202
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: YQ1SvejwGmf4XvrUSHIIJiSUZynGj4uPUx2K7vxKcjNCmoV2SJnbEFok+Md1hNfL
X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7334
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

On Fri, Mar 03, 2023 at 05:57:41PM +0800, Baolu Lu wrote:
> On 2023/3/3 17:32, Jean-Philippe Brucker wrote:
> > > I suppose the common thing is reserving some kind of special PASIDs.
> > Are you planning to use RID_PASID != 0 in VT-d?  Otherwise we could just
> > communicate min_pasid from the IOMMU driver the same way we do max_pasid.
> > 
> > Otherwise I guess re-introduce a lighter ioasid_alloc() that the IOMMU
> > driver calls to reserve PASID0/RID_PASID.
> 
> Yes. We probably will use a non-zero RID_PASID in the future. An
> interface to reserve (or allocate) a PASID from iommu_global_pasid_ida
> should work then.

Just allowing the driver to store XA_ZERO_ENTRY would be fine

Jason