Message-ID: <1060e7786498f384634b01c335bf7bf43365e1fe.camel@infradead.org>
Subject: Re: IRQ affinity not working on Xen pci-platform device
From:   David Woodhouse <dwmw2@infradead.org>
To:     Thomas Gleixner <tglx@linutronix.de>,
        linux-kernel <linux-kernel@vger.kernel.org>,
        xen-devel <xen-devel@lists.xenproject.org>
Date:   Fri, 03 Mar 2023 16:54:46 +0000
In-Reply-To: <87fsalkcck.ffs@tglx>
References: <07866eaf6354dd43d87cffb6eebf101716845b66.camel@infradead.org>
         <87fsalkcck.ffs@tglx>
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On Fri, 2023-03-03 at 17:51 +0100, Thomas Gleixner wrote:
> David!
>=20
> On Fri, Mar 03 2023 at 15:16, David Woodhouse wrote:
> > I added the 'xen_no_vector_callback' kernel parameter a while back
> > (commit b36b0fe96af) to ensure we could test that more for Linux
> > guests.
> >=20
> > Most of my testing at the time was done with just two CPUs, and I
> > happened to just test it with four. It fails, because the IRQ isn't
> > actually affine to CPU0.
> >=20
> > I tried making it work anyway (in line with the comment in platform-
> > pci.c which says that it shouldn't matter if it *runs* on CPU0 as long
> > as it processes events *for* CPU0). That didn't seem to work.
> >=20
> > If I put the irq_set_affinity() call *before* the request_irq() that
> > does actually work. But it's setting affinity on an IRQ it doesn't even
> > own yet.
>=20
> The core allows it for raisins. See below... :)
>=20
> > Test hacks below; this is testable with today's QEMU master (yay!) and:
> >=20
> > =C2=A0 qemu-system-x86_64 -display none -serial mon:stdio -smp 4 \
> > =C2=A0=C2=A0=C2=A0=C2=A0 -accel kvm,xen-version=3D0x4000a,kernel-irqchi=
p=3Dsplit \
> > =C2=A0=C2=A0=C2=A0=C2=A0 -kernel ~/git/linux/arch/x86/boot//bzImage \
> > =C2=A0=C2=A0=C2=A0=C2=A0 -append "console=3DttyS0,115200 xen_no_vector_=
callback"
> >=20
> > ...
> >=20
> > [=C2=A0=C2=A0=C2=A0 0.577173] ACPI: \_SB_.LNKC: Enabled at IRQ 11
> > [=C2=A0=C2=A0=C2=A0 0.578149] The affinity mask was 0-3
> > [=C2=A0=C2=A0=C2=A0 0.579081] The affinity mask is 0-3 and the handler =
is on 2
> > [=C2=A0=C2=A0=C2=A0 0.580288] The affinity mask is 0 and the handler is=
 on 2
>=20
> What happens is that once the interrupt is requested, the affinity
> setting is deferred to the first interrupt. See the marvelous dance in
> arch/x86/kernel/apic/msi.c::msi_set_affinity().
>=20
> If you do the setting before request_irq() then the startup will assign
> it to the target mask right away.
>=20
> Btw, you are using irq_get_affinity_mask(), which gives you the desired
> target mask. irq_get_effective_affinity_mask() gives you the real one.
>=20
> Can you verify that the thing moves over after the first interrupt or is
> that too late already?

It doesn't seem to move. The hack to just return IRQ_NONE if invoked on
CPU !=3D 0 was intended to do just that. It's a level-triggered interrupt
so when the handler does nothing on the "wrong" CPU, it ought to get
invoked again on the *correct* CPU and actually=C2=A0work that time.

But no, as the above logs show, it gets invoked twice *both* on CPU2.

If I do the setting before request_irq() then it should assign it right
away (unless that IRQ was already in use? It's theoretically a shared
PCI INTx line). But even then, that would mean I'm messing with
affinity on an IRQ I haven't even requested yet and don't own?

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