Message-ID: <9093ee69-eee3-7a6c-794e-3df2be11496e@starfivetech.com>
Date:   Mon, 6 Mar 2023 10:19:17 +0800
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Subject: Re: [PATCH v5 05/12] riscv: dts: starfive: jh7110: Add ethernet
 device nodes
To:     Andrew Lunn <andrew@lunn.ch>
CC:     <linux-riscv@lists.infradead.org>, <netdev@vger.kernel.org>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        "David S . Miller" <davem@davemloft.net>,
        Eric Dumazet <edumazet@google.com>,
        "Jakub Kicinski" <kuba@kernel.org>,
        Paolo Abeni <pabeni@redhat.com>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Emil Renner Berthing <kernel@esmil.dk>,
        Richard Cochran <richardcochran@gmail.com>,
        Heiner Kallweit <hkallweit1@gmail.com>,
        Peter Geis <pgwipeout@gmail.com>,
        Yanhong Wang <yanhong.wang@starfivetech.com>
References: <20230303085928.4535-1-samin.guo@starfivetech.com>
 <20230303085928.4535-6-samin.guo@starfivetech.com> <ZAH6CGoXBKz0FmW3@lunn.ch>
Content-Language: en-US
From:   Guo Samin <samin.guo@starfivetech.com>
In-Reply-To: <ZAH6CGoXBKz0FmW3@lunn.ch>
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Precedence: bulk


在 2023/3/3 21:45:44, Andrew Lunn 写道:
>> +		gmac0: ethernet@16030000 {
>> +			compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
>> +			reg = <0x0 0x16030000 0x0 0x10000>;
>> +			clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>,
>> +				 <&aoncrg JH7110_AONCLK_GMAC0_AHB>,
>> +				 <&syscrg JH7110_SYSCLK_GMAC0_PTP>,
>> +				 <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>,
>> +				 <&syscrg JH7110_SYSCLK_GMAC0_GTXC>;
>> +			clock-names = "stmmaceth", "pclk", "ptp_ref",
>> +				      "tx", "gtx";
>> +			resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>,
>> +				 <&aoncrg JH7110_AONRST_GMAC0_AHB>;
>> +			reset-names = "stmmaceth", "ahb";
>> +			interrupts = <7>, <6>, <5>;
>> +			interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
>> +			phy-mode = "rgmii-id";
> 
> phy-mode is a board property, not a SoC property. It should be in the
> board .dts file, not the SoC .dtsi file.

Thanks. I will fix it in the next version.
> 
>> +			snps,multicast-filter-bins = <64>;
>> +			snps,perfect-filter-entries = <8>;
>> +			rx-fifo-depth = <2048>;
>> +			tx-fifo-depth = <2048>;
>> +			snps,fixed-burst;
>> +			snps,no-pbl-x8;
>> +			snps,force_thresh_dma_mode;
>> +			snps,axi-config = <&stmmac_axi_setup>;
>> +			snps,tso;
>> +			snps,en-tx-lpi-clockgating;
>> +			snps,txpbl = <16>;
>> +			snps,rxpbl = <16>;
>> +			status = "disabled";
>> +			phy-handle = <&phy0>;
> 
> The PHY is external, so this is also a board property, not a SoC
> property. 
Will fix, thanks.
> 
>> +
>> +			mdio {
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +				compatible = "snps,dwmac-mdio";
>> +
>> +				phy0: ethernet-phy@0 {
>> +					reg = <0>;
>> +				};
> 
> The PHY is also a board property. You could for example design a board
> where both PHYs are on one MDIO bus, in order to save two SoC pins.

Sounds like a good idea.
> 
>       Andrew

Thank you for taking the time to review.
-- 
Best regards,
Samin