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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id e13-20020adff34d000000b002c53cc7504csm9525832wrp.78.2023.03.06.03.34.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Mar 2023 03:34:24 -0800 (PST) References: <20230301183759.16163-1-ddrokosov@sberdevices.ru> <20230301183759.16163-4-ddrokosov@sberdevices.ru> User-agent: mu4e 1.8.13; emacs 28.2 From: Jerome Brunet To: Dmitry Rokosov , neil.armstrong@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, khilman@baylibre.com, martin.blumenstingl@googlemail.com Cc: jian.hu@amlogic.com, kernel@sberdevices.ru, rockosov@gmail.com, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v9 3/5] dt-bindings: clock: meson: add A1 PLL clock controller bindings Date: Mon, 06 Mar 2023 12:33:48 +0100 In-reply-to: <20230301183759.16163-4-ddrokosov@sberdevices.ru> Message-ID: <1jmt4qazb3.fsf@starbuckisacylon.baylibre.com> MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed 01 Mar 2023 at 21:37, Dmitry Rokosov wrote: > Add the documentation for Amlogic A1 PLL clock driver, and A1 PLL > clock controller bindings. > Also include new A1 clock controller dt bindings to MAINTAINERS. > > Signed-off-by: Jian Hu > Signed-off-by: Dmitry Rokosov patch order is wrong. Bindings before drivers please. > --- > .../bindings/clock/amlogic,a1-pll-clkc.yaml | 59 +++++++++++++++++++ > MAINTAINERS | 1 + > include/dt-bindings/clock/a1-pll-clkc.h | 20 +++++++ > 3 files changed, 80 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml > create mode 100644 include/dt-bindings/clock/a1-pll-clkc.h > > diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml > new file mode 100644 > index 000000000000..8bd2c948df86 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml > @@ -0,0 +1,59 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/amlogic,a1-pll-clkc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Amlogic Meson A/C serials PLL Clock Control Unit > + > +maintainers: > + - Neil Armstrong > + - Jerome Brunet > + - Jian Hu > + - Dmitry Rokosov > + > +properties: > + compatible: > + const: amlogic,a1-pll-clkc > + > + '#clock-cells': > + const: 1 > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: input fixpll_in > + - description: input hifipll_in > + > + clock-names: > + items: > + - const: fixpll_in > + - const: hifipll_in > + > +required: > + - compatible > + - '#clock-cells' > + - reg > + - clocks > + - clock-names > + > +additionalProperties: false > + > +examples: > + - | > + #include > + apb { > + #address-cells = <2>; > + #size-cells = <2>; > + > + clock-controller@7c80 { > + compatible = "amlogic,a1-pll-clkc"; > + reg = <0 0x7c80 0 0x18c>; > + #clock-cells = <1>; > + clocks = <&clkc_periphs CLKID_FIXPLL_IN>, > + <&clkc_periphs CLKID_HIFIPLL_IN>; > + clock-names = "fixpll_in", "hifipll_in"; > + }; > + }; > diff --git a/MAINTAINERS b/MAINTAINERS > index 39ff1a717625..8438bc9bd636 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -1895,6 +1895,7 @@ L: linux-amlogic@lists.infradead.org > S: Maintained > F: Documentation/devicetree/bindings/clock/amlogic* > F: drivers/clk/meson/ > +F: include/dt-bindings/clock/a1* > F: include/dt-bindings/clock/gxbb* > F: include/dt-bindings/clock/meson* > > diff --git a/include/dt-bindings/clock/a1-pll-clkc.h b/include/dt-bindings/clock/a1-pll-clkc.h > new file mode 100644 > index 000000000000..3a559518c6e6 > --- /dev/null > +++ b/include/dt-bindings/clock/a1-pll-clkc.h > @@ -0,0 +1,20 @@ > +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ > +/* > + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. > + * Author: Jian Hu > + * > + * Copyright (c) 2023, SberDevices. All Rights Reserved. > + * Author: Dmitry Rokosov > + */ > + > +#ifndef __A1_PLL_CLKC_H > +#define __A1_PLL_CLKC_H > + > +#define CLKID_FIXED_PLL 1 > +#define CLKID_FCLK_DIV2 6 > +#define CLKID_FCLK_DIV3 7 > +#define CLKID_FCLK_DIV5 8 > +#define CLKID_FCLK_DIV7 9 > +#define CLKID_HIFI_PLL 10 > + > +#endif /* __A1_PLL_CLKC_H */