Message-ID: <785e0072-b9a1-38d5-cefc-67accf77d705@quicinc.com>
Date:   Mon, 6 Mar 2023 20:44:39 +0530
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Subject: Re: [PATCH 5/6] ARM: dts: qcom: sdx65-mtp: Enable PCIE0 PHY
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To:     Konrad Dybcio <konrad.dybcio@linaro.org>, <agross@kernel.org>,
        <andersson@kernel.org>, <lee@kernel.org>, <robh+dt@kernel.org>,
        <krzysztof.kozlowski+dt@linaro.org>, <mani@kernel.org>,
        <lpieralisi@kernel.org>, <kw@linux.com>, <bhelgaas@google.com>,
        <manivannan.sadhasivam@linaro.org>
CC:     <linux-arm-msm@vger.kernel.org>, <devicetree@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>
References: <1678080302-29691-1-git-send-email-quic_rohiagar@quicinc.com>
 <1678080302-29691-6-git-send-email-quic_rohiagar@quicinc.com>
 <f2660adc-e6c8-9de6-e1d6-7abdc7ad7249@linaro.org>
From:   Rohit Agarwal <quic_rohiagar@quicinc.com>
In-Reply-To: <f2660adc-e6c8-9de6-e1d6-7abdc7ad7249@linaro.org>
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On 3/6/2023 4:00 PM, Konrad Dybcio wrote:
>
> On 6.03.2023 06:25, Rohit Agarwal wrote:
>> Enable PCIE0 PHY on SDX65 MTP for PCIE EP.
>>
>> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
>> ---
> Status should go last. It would be nice if you could update
> that for the other nodes in this dt while at it.

Yes, Surely will do.

Thanks,
Rohit.
>
> Konrad
>>   arch/arm/boot/dts/qcom-sdx65-mtp.dts | 7 +++++++
>>   1 file changed, 7 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
>> index 85ea02d..86bb853 100644
>> --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts
>> +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
>> @@ -245,6 +245,13 @@
>>   	status = "okay";
>>   };
>>   
>> +&pcie0_phy {
>> +	status = "okay";
>> +
>> +	vdda-phy-supply = <&vreg_l1b_1p2>;
>> +	vdda-pll-supply = <&vreg_l4b_0p88>;
>> +};
>> +
>>   &qpic_bam {
>>   	status = "okay";
>>   };