Date:   Mon, 6 Mar 2023 22:35:01 +0000
From:   Conor Dooley <conor@kernel.org>
To:     Stephen Boyd <sboyd@kernel.org>
Cc:     Jesse Taube <mr.bossman075@gmail.com>,
        linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org,
        linux-kernel@vger.kernel.org, Yimin Gu <ustcymgu@gmail.com>,
        Damien Le Moal <damien.lemoal@wdc.com>,
        Michael Turquette <mturquette@baylibre.com>,
        Waldemar Brodkorb <wbx@openadk.org>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Conor Dooley <conor.dooley@microchip.com>,
        kernel test robot <lkp@intel.com>
Subject: Re: [PATCH v3 1/3] clk: k210: remove an implicit 64-bit division
Message-ID: <be589843-dfc1-47dc-a488-a4fad645c638@spud>
References: <20230301002657.352637-1-Mr.Bossman075@gmail.com>
 <20230301002657.352637-2-Mr.Bossman075@gmail.com>
 <3b0a1481873a2a7c26015fcedcc673b3.sboyd@kernel.org>
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On Mon, Mar 06, 2023 at 02:31:00PM -0800, Stephen Boyd wrote:
> Quoting Jesse Taube (2023-02-28 16:26:55)
> > diff --git a/drivers/clk/clk-k210.c b/drivers/clk/clk-k210.c
> > index 67a7cb3503c3..4eed667eddaf 100644
> > --- a/drivers/clk/clk-k210.c
> > +++ b/drivers/clk/clk-k210.c
> > @@ -495,7 +495,7 @@ static unsigned long k210_pll_get_rate(struct clk_h=
w *hw,
> >         f =3D FIELD_GET(K210_PLL_CLKF, reg) + 1;
> >         od =3D FIELD_GET(K210_PLL_CLKOD, reg) + 1;
> > =20
> > -       return (u64)parent_rate * f / (r * od);
> > +       return div_u64((u64)parent_rate * f, r * od);
>=20
> The equation 'r * od' can't overflow 32-bits, right?

Yah, I checked that when writing the patch. They're 4-bit fields:
> /*
>  * PLL control register bits.
>  */
> #define K210_PLL_CLKR		GENMASK(3, 0)
> #define K210_PLL_CLKF		GENMASK(9, 4)
> #define K210_PLL_CLKOD		GENMASK(13, 10)

Cheers,
Conor.


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