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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT047.mail.protection.outlook.com (10.13.172.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6156.21 via Frontend Transport; Tue, 7 Mar 2023 02:16:53 +0000 Received: from platform-dev1.pensando.io (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 6 Mar 2023 20:16:50 -0600 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v10 05/15] dt-bindings: soc: amd: amd,pensando-elbasr: Add AMD Pensando SoC System Controller Date: Mon, 6 Mar 2023 18:16:43 -0800 Message-ID: <20230307021643.25938-1-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <52fb81e2-0d9b-600d-42af-1405fdd6509b@linaro.org> References: <52fb81e2-0d9b-600d-42af-1405fdd6509b@linaro.org> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT047:EE_|CY5PR12MB6129:EE_ X-MS-Office365-Filtering-Correlation-Id: 2c9f9dd0-4aef-4cb4-3bd6-08db1eb204b2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Mar 2023 02:16:53.4077 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2c9f9dd0-4aef-4cb4-3bd6-08db1eb204b2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT047.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6129 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 06/03/2023 8:35, Krzysztof Kozlowski wrote: > On 06/03/2023 05:07, Brad Larson wrote: >> Support the AMD Pensando SoC Controller which is a SPI connected device >> providing a miscellaneous set of essential board control/status registers. >> This device is present in all Pensando SoC based designs. >> >> Signed-off-by: Brad Larson >> --- >> >> v10 changes: >> - Property renamed to amd,pensando-ctrl >> - Driver is renamed and moved to soc/drivers/amd affecting binding >> - Delete cs property, driver handles device node creation from parent num-cs >> fixing schema reg error in a different way >> >> v9 changes: >> - Instead of four nodes, one per chip-select, a single >> node is used with reset-cells in the parent. >> - No MFD API is used anymore in the driver so it made >> sense to move this to drivers/spi. >> - This driver is common for all Pensando SoC based designs >> so changed the name to pensando-sr.c to not make it Elba >> SoC specific. >> - Added property cs for the chip-select number which is used >> by the driver to create /dev/pensr0. >> >> --- >> .../bindings/soc/amd/amd,pensando-ctrl.yaml | 60 +++++++++++++++++++ >> 1 file changed, 60 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/soc/amd/amd,pensando-ctrl.yaml >> >> diff --git a/Documentation/devicetree/bindings/soc/amd/amd,pensando-ctrl.yaml b/Documentation/devicetree/bindings/soc/amd/amd,pensando-ctrl.yaml >> new file mode 100644 >> index 000000000000..36694077b2e6 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/soc/amd/amd,pensando-ctrl.yaml > > Your subject suggests this is pensando-elbasr but you write everywhere > pensando-ctrl. Confusing. Pick one. I'll fix the commit message. This driver is common across multiple Pensando SoCs and embedding elba in the name is misleading which is why I changed it to pensando controller (pensando-ctrl). Sorry for the churn. >> @@ -0,0 +1,60 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/soc/amd/amd,pensando-ctrl.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: AMD Pensando SoC Controller >> + >> +description: | > > No need for | Removed | >> + The AMD Pensando SoC Controller is a SPI connected device with essential >> + control/status registers accessed on chip select 0. This device is present >> + in all Pensando SoC based designs. >> + >> +maintainers: >> + - Brad Larson >> + >> +properties: >> + compatible: >> + contains: > > Drop 'contains'. That's not a correct syntax here. > Removed contains and looks like this now: properties: compatible: enum: - amd,pensando-ctrl >> + enum: >> + - amd,pensando-ctrl >> + >> + reg: >> + minItems: 1 > > maxItems instead Changed to maxItems: 1 >> + >> + '#reset-cells': >> + const: 1 >> + >> + interrupts: >> + maxItems: 1 >> + >> + spi-max-frequency: true > > Drop, not needed. > Removed spi-max-frequency and included alOff w/spi-peripheral-props.yaml >> + >> +required: >> + - compatible >> + - spi-max-frequency >> + - '#reset-cells' > > allOf with ref to spi-peripheral-props.yaml > >> + >> +unevaluatedProperties: false > > This is not correct without allOf (should be additionalProperties if you > are not using allOf), which leads you to the missing allOf. Thanks for pointing out use of spi-peripheral-props.yaml, looks like this now +required: + - compatible + - reg + - '#reset-cells' + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false >> + >> +examples: >> + - | >> + #include >> + >> + spi { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + num-cs = <4>; > > Drop num-cs, not important in this context. Removed num-cs >> + >> + system-controller@0 { >> + compatible = "amd,pensando-ctrl"; >> + reg = <0>; >> + spi-max-frequency = <12000000>; >> + interrupt-parent = <&porta>; >> + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; >> + #reset-cells = <1>; >> + }; >> + }; >> + >> +... Regards, Brad