Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BAB0FC678D4 for ; Tue, 7 Mar 2023 14:11:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229972AbjCGOLN (ORCPT ); Tue, 7 Mar 2023 09:11:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49086 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230515AbjCGOJp (ORCPT ); Tue, 7 Mar 2023 09:09:45 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CB60D85A56 for ; Tue, 7 Mar 2023 06:08:24 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 118EF61456 for ; Tue, 7 Mar 2023 14:08:20 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 80D9EC433A4; Tue, 7 Mar 2023 14:08:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1678198099; bh=1Pv62B1bCqgAyF8KhSQC3DpGFth7DQJv+JqkdwKA/P8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ub98OoZAczjx5df73sZsoMHG9cjxGO/uF8C5atheU3gDlrpNMJU1glWwS7UYuwabn e9o+31uQNbmEy5UFteDabiQoUWOe1wG/YShLWi6prDCQKpUitSLbABA0TYdduW8EzV v1u/hfN8ORwsX/1Fgp6p2MvElkpRnhOm7jCeBZuitf/NLspLbIWNlT0x+RbAh6UpSc wRKfAdDf6KO3zKwI5gAjvB5SAzXnKpT6ZbhydJF+ojlk6cvtoW/p8lhRJLTk5ipi4x i9UftwaJy7Pl0/aF/xB7tuRhgTDHXWsqFxEZ7S9USFoOsxJpWYrBAT/k/EBta/L4wT bAJmJGExIvxiw== From: Ard Biesheuvel To: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Ard Biesheuvel , Catalin Marinas , Will Deacon , Marc Zyngier , Mark Rutland , Ryan Roberts , Anshuman Khandual , Kees Cook Subject: [PATCH v3 42/60] arm64/mm: Add FEAT_LPA2 specific ID_AA64MMFR0.TGRAN[2] Date: Tue, 7 Mar 2023 15:05:04 +0100 Message-Id: <20230307140522.2311461-43-ardb@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230307140522.2311461-1-ardb@kernel.org> References: <20230307140522.2311461-1-ardb@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1728; i=ardb@kernel.org; h=from:subject; bh=86yHI17InXfad8HaTxgE2bN7oLspaaBMytfB+uKkgcI=; b=owGbwMvMwCFmkMcZplerG8N4Wi2JIYXdJS+O8eZEv2X/L/Y5MbWeW521bcuZeZfunv06I2wxw 5Zpyn7HOkpZGMQ4GGTFFFkEZv99t/P0RKla51myMHNYmUCGMHBxCsBEJAoZ/ideMRLnjWy/udRo fXFwTMlL/78FVRWmyscmb3TIEn/NcYGR4fSpLbL1k9bMDer1u/C4uXxvwLOi9uUNz5g7iv+yi7N M4AAA X-Developer-Key: i=ardb@kernel.org; a=openpgp; fpr=F43D03328115A198C90016883D200E9CA6329909 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Anshuman Khandual PAGE_SIZE support is tested against possible minimum and maximum values for its respective ID_AA64MMFR0.TGRAN field, depending on whether it is signed or unsigned. But then FEAT_LPA2 implementation needs to be validated for 4K and 16K page sizes via feature specific ID_AA64MMFR0.TGRAN values. Hence it adds FEAT_LPA2 specific ID_AA64MMFR0.TGRAN[2] values per ARM ARM (0487G.A). Acked-by: Catalin Marinas Signed-off-by: Anshuman Khandual Signed-off-by: Ard Biesheuvel --- arch/arm64/include/asm/sysreg.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 9e3ecba3c4e67936..21f2ceeb2d152469 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -630,11 +630,13 @@ #if defined(CONFIG_ARM64_4K_PAGES) #define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN4_SHIFT +#define ID_AA64MMFR0_EL1_TGRAN_LPA2 ID_AA64MMFR0_EL1_TGRAN4_52_BIT #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT #elif defined(CONFIG_ARM64_16K_PAGES) #define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN16_SHIFT +#define ID_AA64MMFR0_EL1_TGRAN_LPA2 ID_AA64MMFR0_EL1_TGRAN16_52_BIT #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT -- 2.39.2