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Peter Anvin" , Peter Zijlstra , "corbet@lwn.net" , "vkoul@kernel.org" , "dmaengine@vger.kernel.org" , "linux-doc@vger.kernel.org" , Robin Murphy , Will Deacon , David Woodhouse , "Raj, Ashok" , "Liu, Yi L" , "Yu, Fenghua" , "Jiang, Dave" , Kirill Shutemov Subject: RE: [PATCH v4 3/6] iommu/sva: Stop using ioasid_set for SVA Thread-Topic: [PATCH v4 3/6] iommu/sva: Stop using ioasid_set for SVA Thread-Index: AQHZTJj76eQP8uX72EyfrDQEvPOjua7ndRIAgABHXYCAAJj+AIAAd42AgAAHA4CAADdXgIAGk7qAgADnasA= Date: Wed, 8 Mar 2023 07:32:31 +0000 Message-ID: References: <20230301235646.2692846-1-jacob.jun.pan@linux.intel.com> <20230301235646.2692846-4-jacob.jun.pan@linux.intel.com> <3b7fb4d3-1fe9-a3be-46ad-c271be9f96c7@linux.intel.com> <20230302091707.58d59964@jacob-builder> <794c7dad-2e62-3afa-ea10-92179b0d1659@linux.intel.com> <20230303093235.GB361458@myrica> <3b2c6fe9-821f-9b84-acb6-777e8517a0fc@linux.intel.com> <20230307094203.4dc51ff4@jacob-builder> In-Reply-To: <20230307094203.4dc51ff4@jacob-builder> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BN9PR11MB5276.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: b7e59ad2-5fd8-4d95-4e47-08db1fa7470d X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Mar 2023 07:32:31.4955 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: c8CA4JWWCDEzrzBFM8aplbYnV/wT9ufTsNMhSOKCz7JTN21N0qy6dLCiapfqejnfFtz0Hiwf4KoPcr1aR1DTxw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR11MB6720 X-OriginatorOrg: intel.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > From: Jacob Pan > Sent: Wednesday, March 8, 2023 1:42 AM >=20 > Hi Jason, >=20 > On Fri, 3 Mar 2023 09:15:45 -0400, Jason Gunthorpe > wrote: >=20 > > On Fri, Mar 03, 2023 at 05:57:41PM +0800, Baolu Lu wrote: > > > On 2023/3/3 17:32, Jean-Philippe Brucker wrote: > > > > > I suppose the common thing is reserving some kind of special > > > > > PASIDs. > > > > Are you planning to use RID_PASID !=3D 0 in VT-d? Otherwise we cou= ld > > > > just communicate min_pasid from the IOMMU driver the same way we > do > > > > max_pasid. > > > > > > > > Otherwise I guess re-introduce a lighter ioasid_alloc() that the IO= MMU > > > > driver calls to reserve PASID0/RID_PASID. > > > > > > Yes. We probably will use a non-zero RID_PASID in the future. An > > > interface to reserve (or allocate) a PASID from iommu_global_pasid_id= a > > > should work then. > > > > Just allowing the driver to store XA_ZERO_ENTRY would be fine > > > So we provide APIs for both? > 1. alloc a global PASID, returned by this API > 2. try to reserve a global PASID given by the driver, i.e. > xa_cmpxchg(&iommu_global_pasid_ida.xa, 2, NULL, > XA_ZERO_ENTRY, > GFP_KERNEL); > seems #1 is sufficient. >=20 No need for both. There will be on-demand allocation on this global space so a reservation interface doesn't make sense.