Message-ID: <e52f36336d849c46b0ee2196f88c3490ddd34323.camel@infradead.org>
Subject: Re: [PATCH v13 00/11] Parallel CPU bringup for x86_64
From:   David Woodhouse <dwmw2@infradead.org>
To:     Sean Christopherson <seanjc@google.com>
Cc:     Tom Lendacky <thomas.lendacky@amd.com>,
        Usama Arif <usama.arif@bytedance.com>, tglx@linutronix.de,
        kim.phillips@amd.com, brgerst@gmail.com,
        Sabin Rapan <sabrapan@amazon.com>, piotrgorski@cachyos.org,
        oleksandr@natalenko.name, arjan@linux.intel.com, mingo@redhat.com,
        bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com,
        x86@kernel.org, pbonzini@redhat.com, paulmck@kernel.org,
        linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
        rcu@vger.kernel.org, mimoja@mimoja.de, hewenliang4@huawei.com,
        pmenzel@molgen.mpg.de, fam.zheng@bytedance.com,
        punit.agrawal@bytedance.com, simon.evans@bytedance.com,
        liangma@liangbit.com
Date:   Wed, 08 Mar 2023 07:38:32 +0000
In-Reply-To: <ZAfDhT97ctXSYiYe@google.com>
References: <20230302111227.2102545-1-usama.arif@bytedance.com>
         <faa0eb3bb8ba0326d501516a057ab46eaf1f3c05.camel@infradead.org>
         <effbb6e2-c5a1-af7f-830d-8d7088f57477@amd.com>
         <269ed38b5eed9c3a259c183d59d4f1eb5128f132.camel@infradead.org>
         <0c56683a-c258-46f6-056e-e85da8a557db@amd.com>
         <3bfbbd92-b2ed-8189-7b57-0533f6c87ae7@amd.com>
         <1975308c952236895f2d8f0e56af9db288eaf330.camel@infradead.org>
         <ZAfDhT97ctXSYiYe@google.com>
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On Tue, 2023-03-07 at 15:35 -0800, Sean Christopherson wrote:
> On Tue, Mar 07, 2023, David Woodhouse wrote:
> > On Tue, 2023-03-07 at 16:22 -0600, Tom Lendacky wrote:
> > >=20
> > > I did some Qemu/KVM testing. One thing I noticed is that on AMD, CPUI=
D 0xB=20
> > > EAX will be non-zero only if SMT is enabled. So just booting some gue=
sts=20
> > > without CPU topology never did parallel booting ("smpboot: Disabling=
=20
> > > parallel bringup because CPUID 0xb looks untrustworthy"). I would ima=
gine=20
> > > a bare-metal system that has diabled SMT will not do parallel booting=
, too=20
> > > (but I haven't had time to test that).
> >=20
> > Interesting, thanks. Should I change to checking for *both* EAX and EBX
> > being zero? That's what I did first, after reading only the Intel SDM.
> > But I changed to only EAX because the AMD doc only says that EAX will
> > be zero for unsupported leaves.
>=20
> LOL, nice.=C2=A0 '0' is a prefectly valid output for the shift if there's=
 exactly one
> CPU at the current level, which is why Intel states that both EAX and EBX=
 are
> cleared.=C2=A0 I assume/hope this is effectively a documentation goof, in=
 that the APM
> assumes that all "real" CPUs that support CPUID 0xB also support sub-func=
tion 0.
>=20
> Nit, the AMD says EAX will be zero for unsupported _levels_.=C2=A0 The di=
stinction
> matters because if the entire leaf is unsupported, AMD behavior is to zer=
o out
> all output registers, even if the input leaf is above the max supported l=
eaf.
>=20
> Anyways, the kernel already sanity checks the outputs on all x86 CPUs, ju=
st
> piggyback that logic, e.g. expose detect_extended_topology_leaf() or so.=
=C2=A0 If AMD
> or a VMM is doing something crazy, the kernel is doomed anyways.

Well, we have to be somewhat careful with that assumption. Turns out
that if CPUID 0xb doesn't have valid data, the kernel *wasn't* doomed
anyway. A bunch of our early "WTF doesn't it work on AMD?" issue with
this series were due to precisely that.

But yeah, check_extended_topology_leaf() does check for EBX being non-
zero, and also for SMT_TYPE being in CH. I'll look at just calling
that; it'll make the mess of if/else in the prepare_parallel_bringup()
function a bit cleaner.


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