Message-ID: <1529493a-67f6-4a0b-5ba2-595371cb690a@linaro.org>
Date:   Wed, 8 Mar 2023 09:11:20 +0100
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Reply-To: neil.armstrong@linaro.org
Subject: Re: [PATCH 1/2] arm64: dts: qcom: sm8350: Mark UFS controller as
 cache coherent
Content-Language: en-US
To:     Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
        andersson@kernel.org, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org
Cc:     konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
References: <20230307153201.180626-1-manivannan.sadhasivam@linaro.org>
From:   Neil Armstrong <neil.armstrong@linaro.org>
Organization: Linaro Developer Services
In-Reply-To: <20230307153201.180626-1-manivannan.sadhasivam@linaro.org>
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On 07/03/2023 16:32, Manivannan Sadhasivam wrote:
> The UFS controller on SM8350 supports cache coherency, hence add the
> "dma-coherent" property to mark it as such.
> 
> Fixes: 59c7cf814783 ("arm64: dts: qcom: sm8350: Add UFS nodes")
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
>   arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> index 1c97e28da6ad..1a5a612d4234 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> @@ -1664,6 +1664,7 @@ ufs_mem_hc: ufshc@1d84000 {
>   			power-domains = <&gcc UFS_PHY_GDSC>;
>   
>   			iommus = <&apps_smmu 0xe0 0x0>;
> +			dma-coherent;
>   
>   			clock-names =
>   				"core_clk",

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>