Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE744C678D5 for ; Wed, 8 Mar 2023 12:20:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229492AbjCHMUw (ORCPT ); Wed, 8 Mar 2023 07:20:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38164 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231312AbjCHMUX (ORCPT ); Wed, 8 Mar 2023 07:20:23 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2D2C39E51F; Wed, 8 Mar 2023 04:20:17 -0800 (PST) Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32853GTb022514; Wed, 8 Mar 2023 12:20:09 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=qcppdkim1; bh=+e/H92uUJNx92Ro/yEJ/LS8VqC2wZgo72OrZ/DH5Ixc=; b=m9p9x0vwB3IOA0Is2n9o7dr0mOfYAOA70rIZU2DGDE1XVMM7SXdJ0BD0aghhfd9HYTqX CIqWEOJyH64uoIrZ/k7KuTKRpSn8Sl/WwYOCfxmSeuVgZdVg9G/qomQp67gjyCSnICj6 U6LK2gL3OmjF2GhjzUYh468YYtujHlf464qqdCBA02FMtb2iHEqc5Zd97zwzXxkZf3wv sNAWWGpOsn5m2qJyk5Cjh9SqPo2/V+K61xm5nEcFPdObs/9TfwdeIdZkXy9BOTDuHKZI vCa3mnvWkKnezldw1eU7QLOHF4dqN1lqmyVZCpEz+myubUTaTlrWsbEW1P8kMe1uZpTS pw== Received: from apblrppmta01.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3p6fga1ju7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 08 Mar 2023 12:20:09 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 328CK6rh031435; Wed, 8 Mar 2023 12:20:06 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 3p4fgkn0c7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Wed, 08 Mar 2023 12:20:06 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 328CK5i8031421; Wed, 8 Mar 2023 12:20:05 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-rohiagar-hyd.qualcomm.com [10.213.106.138]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 328CK5dv031410; Wed, 08 Mar 2023 12:20:05 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 98F6A4F94; Wed, 8 Mar 2023 17:50:04 +0530 (+0530) From: Rohit Agarwal To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, lee@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mani@kernel.org, lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com, manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Rohit Agarwal Subject: [PATCH v2 3/6] ARM: dts: qcom: sdx65: Add support for PCIe PHY Date: Wed, 8 Mar 2023 17:49:50 +0530 Message-Id: <1678277993-18836-4-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1678277993-18836-1-git-send-email-quic_rohiagar@quicinc.com> References: <1678277993-18836-1-git-send-email-quic_rohiagar@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 5ZdBE2YwwSZ4_Z4Q4vic2FjMf0PQokbX X-Proofpoint-ORIG-GUID: 5ZdBE2YwwSZ4_Z4Q4vic2FjMf0PQokbX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-08_07,2023-03-08_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 suspectscore=0 spamscore=0 mlxscore=0 clxscore=1015 mlxlogscore=999 impostorscore=0 bulkscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2303080106 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add devicetree support for PCIe PHY used in SDX65 platform. This PHY is used by the PCIe EP controller. Signed-off-by: Rohit Agarwal --- arch/arm/boot/dts/qcom-sdx65.dtsi | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 192f9f9..df9d428 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -293,6 +293,39 @@ status = "disabled"; }; + pcie_phy: phy@1c06000 { + compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy"; + reg = <0x01c06000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_RCHNG_PHY_CLK>; + <&gcc GCC_PCIE_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe"; + + resets = <&gcc GCC_PCIE_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc PCIE_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x01f40000 0x40000>; -- 2.7.4