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 <ca257415-afd4-155d-bbdb-822f6eedd554@linaro.org>
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From:   Bartosz Golaszewski <brgl@bgdev.pl>
Date:   Wed, 8 Mar 2023 17:02:59 +0100
Message-ID: <CAMRc=MfZCQSsPN7SVXAVAsnRyE1LsszHSG0YuXGz72wwZ5b00w@mail.gmail.com>
Subject: Re: [PATCH v4 7/9] arm64: dts: qcom: sa8775p: add high-speed UART nodes
To:     Konrad Dybcio <konrad.dybcio@linaro.org>
Cc:     Andy Gross <agross@kernel.org>,
        Bjorn Andersson <andersson@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org,
        Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
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On Wed, Mar 8, 2023 at 11:57=E2=80=AFAM Konrad Dybcio <konrad.dybcio@linaro=
.org> wrote:
>
>
>
> On 8.03.2023 11:40, Bartosz Golaszewski wrote:
> > From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> >
> > Add two UART nodes that are known to be used by existing development
> > boards with this SoC.
> >
> > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> > ---
> >  arch/arm64/boot/dts/qcom/sa8775p.dtsi | 31 +++++++++++++++++++++++++++
> >  1 file changed, 31 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dt=
s/qcom/sa8775p.dtsi
> > index 992864e3e0c8..5ebfe8c10eac 100644
> > --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> > @@ -490,6 +490,21 @@ &clk_virt SLAVE_QUP_CORE_1 0>,
> >                               operating-points-v2 =3D <&qup_opp_table_1=
00mhz>;
> >                               status =3D "disabled";
> >                       };
> > +
> > +                     uart12: serial@a94000 {
> > +                             compatible =3D "qcom,geni-uart";
> > +                             reg =3D <0x0 0x00a94000 0x0 0x4000>;
> > +                             interrupts =3D <GIC_SPI 358 IRQ_TYPE_LEVE=
L_HIGH>;
> > +                             clocks =3D <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
> > +                             clock-names =3D "se";
> > +                             interconnects =3D <&clk_virt MASTER_QUP_C=
ORE_1 QCOM_ICC_TAG_ALWAYS
> > +                                              &clk_virt SLAVE_QUP_CORE=
_1 QCOM_ICC_TAG_ALWAYS>,
> > +                                             <&gem_noc MASTER_APPSS_PR=
OC QCOM_ICC_TAG_ALWAYS
> > +                                              &config_noc SLAVE_QUP_1 =
QCOM_ICC_TAG_ALWAYS>;
> > +                             interconnect-names =3D "qup-core", "qup-c=
onfig";
> > +                             power-domains =3D <&rpmhpd SA8775P_CX>;
> > +                             status =3D "disabled";
> > +                     };
> >               };
> >
> >               qupv3_id_2: geniqup@8c0000 {
> > @@ -525,6 +540,22 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
> >                               status =3D "disabled";
> >                       };
> >
> > +                     uart17: serial@88c000 {
> > +                             compatible =3D "qcom,geni-uart";
> > +                             reg =3D <0x0 0x0088c000 0x0 0x4000>;
> > +                             interrupts-extended =3D <&intc GIC_SPI 58=
5 IRQ_TYPE_LEVEL_HIGH>,
> > +                                                   <&tlmm 94 IRQ_TYPE_=
LEVEL_HIGH>;
> This hunk is board-specific and only makes sense if bluetooth
> (or some other "important" peripheral) is connected to this
> uart. Generally the uart interrupt is the one coming from the GIC
> and the other one should probably go to the board dtsi.
>

Right, the second one will be consumed by whatever driver will be
there to control GNSS or bluetooth. I'll drop it in the next spin.

Bart

> Konrad
> > +                             clocks =3D <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
> > +                             clock-names =3D "se";
> > +                             interconnects =3D <&clk_virt MASTER_QUP_C=
ORE_2 QCOM_ICC_TAG_ALWAYS
> > +                                              &clk_virt SLAVE_QUP_CORE=
_2 QCOM_ICC_TAG_ALWAYS>,
> > +                                             <&gem_noc MASTER_APPSS_PR=
OC QCOM_ICC_TAG_ALWAYS
> > +                                              &config_noc SLAVE_QUP_2 =
QCOM_ICC_TAG_ALWAYS>;
> > +                             interconnect-names =3D "qup-core", "qup-c=
onfig";
> > +                             power-domains =3D <&rpmhpd SA8775P_CX>;
> > +                             status =3D "disabled";
> > +                     };
> > +
> >                       i2c18: i2c@890000 {
> >                               compatible =3D "qcom,geni-i2c";
> >                               reg =3D <0x0 0x00890000 0x0 0x4000>;