Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99867C678D5 for ; Wed, 8 Mar 2023 16:23:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229929AbjCHQXr (ORCPT ); Wed, 8 Mar 2023 11:23:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34920 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229785AbjCHQXo (ORCPT ); Wed, 8 Mar 2023 11:23:44 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 76C6F968DE; Wed, 8 Mar 2023 08:23:34 -0800 (PST) Date: Wed, 08 Mar 2023 16:23:31 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1678292612; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=HFiuzNGyE2MZXTYS92ORAfHaB7tViY38+H5/LASSeFE=; b=rujE64cWGq/lI9JQ3b7cvWDOVa0reaCVYUt1QLiUkeDAsgNlaSl7hAxe1ZHMQ2sr4RFOHL xwd7yNmhO9SRz94a5088DPKZAiLTLJw9NBvL/X7R9uaWlAyDmlr71/mZQLY16jNvqsDh7M BHFZUC7+ohK9cI/UkgdUSzPZTsHjwV4oniFrxCupC0kq3DreitSTnxu5yuAgaQK2hrmVdX lNKGhpWQOMttpgVI0qrlRthGHisyN9YeuQGFn9oL2Y18s3LK8xXawzDBWj4Vb8KPzmapg8 tDExzXENNJspLUWEWwMC4SaMnCc7Yqb8wOz0fyxiF/j2m3CUjntW3E7lU8VcOg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1678292612; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=HFiuzNGyE2MZXTYS92ORAfHaB7tViY38+H5/LASSeFE=; b=lMThGvy+Q1AHni5EPxRNSzMsXbjiev8tM/VtaxRGS4dPQrlUlEZWvgiT+h0lhYuvAOCUKx toIWIGFsAK0jXYAg== From: "tip-bot2 for Andrew Cooper" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/urgent] x86/CPU/AMD: Disable XSAVES on AMD family 0x17 Cc: Tavis Ormandy , Andrew Cooper , "Borislav Petkov (AMD)" , , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20230307174643.1240184-1-andrew.cooper3@citrix.com> References: <20230307174643.1240184-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Message-ID: <167829261190.5837.14765105385267384206.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the x86/urgent branch of tip: Commit-ID: b0563468eeac88ebc70559d52a0b66efc37e4e9d Gitweb: https://git.kernel.org/tip/b0563468eeac88ebc70559d52a0b66efc37e4e9d Author: Andrew Cooper AuthorDate: Tue, 07 Mar 2023 17:46:43 Committer: Borislav Petkov (AMD) CommitterDate: Wed, 08 Mar 2023 16:56:08 +01:00 x86/CPU/AMD: Disable XSAVES on AMD family 0x17 AMD Erratum 1386 is summarised as: XSAVES Instruction May Fail to Save XMM Registers to the Provided State Save Area This piece of accidental chronomancy causes the %xmm registers to occasionally reset back to an older value. Ignore the XSAVES feature on all AMD Zen1/2 hardware. The XSAVEC instruction (which works fine) is equivalent on affected parts. [ bp: Typos, move it into the F17h-specific function. ] Reported-by: Tavis Ormandy Signed-off-by: Andrew Cooper Signed-off-by: Borislav Petkov (AMD) Cc: Link: https://lore.kernel.org/r/20230307174643.1240184-1-andrew.cooper3@citrix.com --- arch/x86/kernel/cpu/amd.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 380753b..95cdd08 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -880,6 +880,15 @@ void init_spectral_chicken(struct cpuinfo_x86 *c) } } #endif + /* + * Work around Erratum 1386. The XSAVES instruction malfunctions in + * certain circumstances on Zen1/2 uarch, and not all parts have had + * updated microcode at the time of writing (March 2023). + * + * Affected parts all have no supervisor XSAVE states, meaning that + * the XSAVEC instruction (which works fine) is equivalent. + */ + clear_cpu_cap(c, X86_FEATURE_XSAVES); } static void init_amd_zn(struct cpuinfo_x86 *c)