From:   David Binderman <dcb314@hotmail.com>
To:     Laurent Pinchart <laurent.pinchart@ideasonboard.com>
CC:     "andrzej.hajda@intel.com" <andrzej.hajda@intel.com>,
        "neil.armstrong@linaro.org" <neil.armstrong@linaro.org>,
        "rfoss@kernel.org" <rfoss@kernel.org>,
        "jonas@kwiboo.se" <jonas@kwiboo.se>,
        "jernej.skrabec@gmail.com" <jernej.skrabec@gmail.com>,
        "airlied@gmail.com" <airlied@gmail.com>,
        "daniel@ffwll.ch" <daniel@ffwll.ch>,
        "dri-devel@lists.freedesktop.org" <dri-devel@lists.freedesktop.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: drivers/gpu/drm/bridge/fsl-ldb.c:101: possible loss of
 information.
Thread-Topic: drivers/gpu/drm/bridge/fsl-ldb.c:101: possible loss of
 information.
Thread-Index: AQHZUROWy83Z6Qqx6EKYMWjImUxUIK7xh4YAgACLKmI=
Date:   Thu, 9 Mar 2023 07:59:34 +0000
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 <20230308232224.GG31765@pendragon.ideasonboard.com>
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Hello there Laurent,=0A=
=0A=
>We could, but I don't think it will make any difference in practice as=0A=
>the maximum pixel clock frequency supported by the SoC is 80MHz (per=0A=
>LVDS channel). That would result in a 560MHz frequency returned by this=0A=
>function, well below the 31 bits limit.=0A=
=0A=
Thanks for your explanation. I have a couple of suggestions for possible im=
provements:=0A=
=0A=
1. Your explanatory text in a comment nearby. This helps all readers of the=
 code.=0A=
=0A=
2. Might the frequency go up to 300 MHz anytime soon ? The code will stop w=
orking then. =0A=
In this case, I would suggest to put in a run time sanity check to make sur=
e no 31 bit overflow. =0A=
=0A=
Just a couple of ideas for the code.=0A=
=0A=
Regards=0A=
=0A=
David Binderman=0A=