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Thu, 9 Mar 2023 17:19:09 -0800 Date: Thu, 9 Mar 2023 17:19:07 -0800 From: Nicolin Chen To: Robin Murphy CC: , , , , , , , , , , Subject: Re: [PATCH v1 13/14] iommu/arm-smmu-v3: Add CMDQ_OP_TLBI_NH_VAA and CMDQ_OP_TLBI_NH_ALL Message-ID: References: <3b059f4b0bda1e83d402248114a774186f678387.1678348754.git.nicolinc@nvidia.com> <510e6e1a-884f-ae5a-35f3-4f4db997abfd@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <510e6e1a-884f-ae5a-35f3-4f4db997abfd@arm.com> X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT077:EE_|PH7PR12MB7985:EE_ X-MS-Office365-Filtering-Correlation-Id: 7a45eb3a-bdbd-44a8-2082-08db210578ea X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: bgDR0ILWxsLIFrO8xzsT/ncqZ/68vryatamC3zSr2XdYN906aNitlTejji/4taKQWSYy8CnN8r8vwblvv1dRDXf6L0FOMTogucdEJK5Q8ndBu1bi4zClq9DrprZKk4xmeVGwt9/RwApUDSmd1vMWkr+lBqzG0fdoCG+odY1V3sCdO6VjpL9XOdVShpLQelxkkVwuWMBES0e9TKPDlCTSgCrf8NveC2UJmi2VQz7iZCJzpRexqSM8bc5yd7wg+IdvrOZszScT3/cxWPl9c/5ODy8CzwT2/JAEHGh5Qaz0syqjO4ON2bX94bdsOOn/FgYWxQF87Mxas2D3IaKghENif80n2KJi4geI8eWjncfU58YqukA9uNAURXK6JGdoOdgDJfXFEZEsbt+PZWHS8IfHqvKoJLmsR44sxjeXW5AoOPh6q3qWB3/QUsJ2dySLVdUIoOdGoORLyJHauhfhOUh8DqR5AyXp4fcEmvDwwAL7b2mBY8bwqNOLoTBySlCuv8HvyH9a3AFcW5d1FWRU/Q0IFPQ7AQf68BNhiqiMmdeZSm+EYCv8WHNtlAJRy194tkGZkAl0BmGuh2doTtCdXlo5b6VZiRCSYfcK5n2RkqZZ62R6rz53Yiq8CUVYxEAN1gKiERTgWXy2yapDEjrmwUVUEZcAtKPYf8VZE9kYY/f2aN//NHYeNyLw/As0k6gJW5F9jl4eIAqJ2kKW8HrSQkIGkbCrKO2AmEksqJoHrerwfq6LG35MDd2DLRPM/XPTZe0vPN4/igSpuR+mXJFkH+0IFw== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230025)(4636009)(39860400002)(396003)(346002)(376002)(136003)(451199018)(36840700001)(40470700004)(46966006)(40460700003)(54906003)(478600001)(316002)(5660300002)(7416002)(8936002)(2906002)(70206006)(8676002)(70586007)(82310400005)(4326008)(41300700001)(6916009)(82740400003)(7636003)(36860700001)(40480700001)(55016003)(86362001)(356005)(186003)(9686003)(33716001)(53546011)(26005)(83380400001)(426003)(336012)(47076005)(67856001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Mar 2023 01:19:18.8813 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7a45eb3a-bdbd-44a8-2082-08db210578ea X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT077.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7985 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Mar 09, 2023 at 01:44:34PM +0000, Robin Murphy wrote: > External email: Use caution opening links or attachments > > > On 2023-03-09 10:53, Nicolin Chen wrote: > > With a nested translation setup, a stage-1 Context Descriptor table can be > > managed by a guest OS in the user space. So, the kernel driver should not > > assume that the guest OS will use a user space device driver that doesn't > > support TLBI_NH_VAA and TLBI_NH_ALL commands. > > > > Add them in the arm_smmu_cmdq_build_cmd(), to prepare for support of these > > two TLBI invalidation requests from the guest level. > > > > Signed-off-by: Nicolin Chen > > --- > > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 4 ++++ > > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 ++ > > 2 files changed, 6 insertions(+) > > > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > index 1f318b5e0921..ac63185ae268 100644 > > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > @@ -277,6 +277,9 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent) > > /* Cover the entire SID range */ > > cmd[1] |= FIELD_PREP(CMDQ_CFGI_1_RANGE, 31); > > break; > > + case CMDQ_OP_TLBI_NH_VAA: > > + ent->tlbi.asid = 0; > > This is backwards - NH_VA is a superset of NH_VAA (not to mention that > quietly modifying the input argument is ugly; in fact it might be nice > if ent was const here). I see. > Please follow the existing pattern, and decouple NH_VA from EL2_VA if > necessary. OK. I was trying to keep it neat, but it looks like decoupling is the right way. Thanks Nic