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Thu, 9 Mar 2023 17:34:16 -0800 Date: Thu, 9 Mar 2023 17:34:14 -0800 From: Nicolin Chen To: Robin Murphy CC: , , , , , , , , , , Subject: Re: [PATCH v1 12/14] iommu/arm-smmu-v3: Support IOMMU_DOMAIN_NESTED type of allocations Message-ID: References: <20fb0697-fc0d-daab-2517-7bee7415e695@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20fb0697-fc0d-daab-2517-7bee7415e695@arm.com> X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT047:EE_|PH7PR12MB6659:EE_ X-MS-Office365-Filtering-Correlation-Id: 59eeb6f3-8530-4988-4f3a-08db2107972c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 5aSAcVPZdVpQQLCbpiuehZh0txs1bRXC63TRvPFl1JJs+LsR2oOk2Pla+olExJz3mA2RvzHHgxs4hbvefwcInTLeK0eH+TfhQKGV/FQS5tvMtxgwVgVCGEC1EkughukofgfKCL/HwYFeneEZF8fZ3U5/Cq4iwh6+s6yKL3RRtscPYD968gMUn8O53dSuZYdumvChjZpmtdV7Nt1WhlkGDZ6s6vbAk74auij9iCMfhvwg2AS9c2/mnP7FJac4Eo/nuxz8vMp4eAJZI3j+db4OqWz4kiqMJjyf36n+HAFc+1HPhSAxfxF5WJPQe2iH3HF+/pbGPnVxd/lz1LQYajYWdD+g/1nnkKl8HBDS0kcC0p6EXm9m8PmH9/1UaHJ50BrAYHWhYNrpxJLuLUK45Bel9ISE3kKQkljwuXI43jXeLwoE1yafnshA35T/brtdv0/TA9pzwDMAT2yaRJRbGjeS3gpmkW9wXug98TftyLmLRuSWMuzUNri5rpPnzvlWnx+X77yUCpJS5s0WVCM+Gwog+yDcAqjhKEllyxtFpj2+38FqMqTbp7TQMgbMxapUkJ4uLMgmhWItN9xTiXkJm2svHlEXwAGfd6Wrtz7tnGzy6XyiCyH9F+25/RQsxdoh1ujklWNO39r3vvoJXWcDOxqpBSe2OWpYwbKFDoDyZ7pyAguXkvPO8ojFTS5RYOHx8iUoPREcpV5ki44uH13v2z9WUz4QIqb7HFrKWhGVCQPHSffK6KNuliVK7McCvflzBbUZY+6LEKT27jXr10+AVagjLA== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230025)(4636009)(346002)(39860400002)(396003)(136003)(376002)(451199018)(36840700001)(40470700004)(46966006)(40460700003)(356005)(54906003)(478600001)(316002)(5660300002)(7416002)(8936002)(2906002)(70586007)(70206006)(8676002)(4326008)(6916009)(41300700001)(82740400003)(7636003)(36860700001)(40480700001)(55016003)(86362001)(9686003)(33716001)(186003)(53546011)(26005)(83380400001)(82310400005)(336012)(426003)(47076005)(473944003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Mar 2023 01:34:28.5933 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 59eeb6f3-8530-4988-4f3a-08db2107972c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT047.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6659 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Mar 09, 2023 at 02:28:09PM +0000, Robin Murphy wrote: > External email: Use caution opening links or attachments > > > On 2023-03-09 13:20, Robin Murphy wrote: > > On 2023-03-09 10:53, Nicolin Chen wrote: > > > Add domain allocation support for IOMMU_DOMAIN_NESTED type. This includes > > > the "finalise" part to log in the user space Stream Table Entry info. > > > > > > Co-developed-by: Eric Auger > > > Signed-off-by: Eric Auger > > > Signed-off-by: Nicolin Chen > > > --- > > > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 38 +++++++++++++++++++-- > > > 1 file changed, 36 insertions(+), 2 deletions(-) > > > > > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > > b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > > index 5ff74edfbd68..1f318b5e0921 100644 > > > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > > @@ -2214,6 +2214,19 @@ static int arm_smmu_domain_finalise(struct > > > iommu_domain *domain, > > > return 0; > > > } > > > + if (domain->type == IOMMU_DOMAIN_NESTED) { > > > + if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1) || > > > + !(smmu->features & ARM_SMMU_FEAT_TRANS_S2)) { > > > + dev_dbg(smmu->dev, "does not implement two stages\n"); > > > + return -EINVAL; > > > + } > > > + smmu_domain->stage = ARM_SMMU_DOMAIN_S1; > > > + smmu_domain->s1_cfg.s1fmt = user_cfg->s1fmt; > > > + smmu_domain->s1_cfg.s1cdmax = user_cfg->s1cdmax; > > > + smmu_domain->s1_cfg.cdcfg.cdtab_dma = user_cfg->s1ctxptr; > > > + return 0; > > > > How's that going to work? If the caller's asked for something we can't > > provide, returning something else and hoping it fails later is not > > sensible, we should just fail right here. It's even more worrying if > > there's a chance it *won't* fail later, and a guest ends up with > > "nested" translation giving it full access to host PA space :/ > > Oops, apologies - in part thanks to the confusing indentation, I managed > to miss the early return and misread this all being under the if > condition for nesting not being supported. Sorry for the confusion :( Perhaps this can help readability, considering that we have multiple places checking the TRANS_S1 and TRANS_S2 features: bool feat_has_s1 smmu->features & ARM_SMMU_FEAT_TRANS_S1; bool feat_has_s2 smmu->features & ARM_SMMU_FEAT_TRANS_S2; if (domain->type == IOMMU_DOMAIN_NESTED) { if (!feat_has_s1 || !feat_has_s2) { dev_dbg(smmu->dev, "does not implement two stages\n"); return -EINVAL; } ... return 0; } if (user_cfg_s2 && !feat_has_s2) return -EINVAL; ... if (!feat_has_s1) smmu_domain->stage = ARM_SMMU_DOMAIN_S2; if (!feat_has_s2) smmu_domain->stage = ARM_SMMU_DOMAIN_S1; Would you like this? Thanks Nic