Message-ID: <139384c3-5ebc-84b6-9109-b98e4690ca68@quicinc.com>
Date:   Fri, 10 Mar 2023 08:44:23 +0530
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Subject: Re: [PATCH 09/15] arm64: dts: qcom: sm6375: Add CPUCP L3 node
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To:     Konrad Dybcio <konrad.dybcio@linaro.org>,
        Amit Kucheria <amitk@kernel.org>,
        Thara Gopinath <thara.gopinath@gmail.com>,
        Andy Gross <agross@kernel.org>,
        Bjorn Andersson <andersson@kernel.org>,
        "Rafael J. Wysocki" <rafael@kernel.org>,
        Daniel Lezcano <daniel.lezcano@linaro.org>,
        Zhang Rui <rui.zhang@intel.com>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Georgi Djakov <djakov@kernel.org>
CC:     <linux-arm-msm@vger.kernel.org>, <linux-pm@vger.kernel.org>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
References: <20230303-topic-sm6375_features0_dts-v1-0-8c8d94fba6f0@linaro.org>
 <20230303-topic-sm6375_features0_dts-v1-9-8c8d94fba6f0@linaro.org>
From:   Sibi Sankar <quic_sibis@quicinc.com>
In-Reply-To: <20230303-topic-sm6375_features0_dts-v1-9-8c8d94fba6f0@linaro.org>
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Precedence: bulk

Hey Konrad,

Thanks for the patch.

On 3/4/23 03:28, Konrad Dybcio wrote:
> Enable the CPUCP block responsible for scaling the L3 cache.

FWIW, the patch just enables the l3 provider, the CPUCP block would
already be up at this point. You would also want to include the
expansion for CPUCP at least once in your patch.

> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com>

> ---
>   arch/arm64/boot/dts/qcom/sm6375.dtsi | 9 +++++++++
>   1 file changed, 9 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi
> index 90f18754a63b..59d7ed25aa36 100644
> --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi
> @@ -1505,6 +1505,15 @@ frame@f42d000 {
>   			};
>   		};
>   
> +		cpucp_l3: interconnect@fd90000 {
> +			compatible = "qcom,sm6375-cpucp-l3", "qcom,epss-l3";
> +			reg = <0 0x0fd90000 0 0x1000>;
> +
> +			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
> +			clock-names = "xo", "alternate";
> +			#interconnect-cells = <1>;
> +		};
> +
>   		cpufreq_hw: cpufreq@fd91000 {
>   			compatible = "qcom,sm6375-cpufreq-epss", "qcom,cpufreq-epss";
>   			reg = <0 0x0fd91000 0 0x1000>, <0 0x0fd92000 0 0x1000>;
>