Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5241C6FD1F for ; Fri, 10 Mar 2023 04:10:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230286AbjCJEKK (ORCPT ); Thu, 9 Mar 2023 23:10:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60948 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230337AbjCJEJN (ORCPT ); Thu, 9 Mar 2023 23:09:13 -0500 Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 314ADF4B59 for ; Thu, 9 Mar 2023 20:09:01 -0800 (PST) Received: by mail-pl1-x634.google.com with SMTP id u5so4300844plq.7 for ; Thu, 09 Mar 2023 20:09:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678421334; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hS/BEmRpdBxk7z2vn4cP+VagM+gkHpiXxJLmHI41D7s=; b=uxYxp0F/05gIQ47D431qZsuL0ZqbDv4S6AOJRgbF/p10t1CxAXIexgDlZyssPyqQJO upkOLJnUn6S3efnNxZYGjsytvJjQqS3s/Osr6ZaO1/O0iX0YDB40opwuBFJ0bF71ejQx iT9mUrgkJl42RZYeJPPAjm6VB2ZSc0RkNPmrJqgV2g68szDQbAK1GqiKAcyxNy/o5FuF zv8/3LmzqSKYgbYs5P1nrb6SfYIhK/1CkmJ2JiNgHIP+tRRZG8Zhfh285EpBhllj1nkm lr1bzbvG58Hc15NSjcwk31bn39380FwPiT/grnNBW7cm2qJoG9Gb3EGKQiyo3VLmo3ax KkaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678421334; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hS/BEmRpdBxk7z2vn4cP+VagM+gkHpiXxJLmHI41D7s=; b=cD1Ct3ljDsafQysHttTiaLOV/aB59kGRwXigD9c8jmjqOXQmki/96eLgqCeI8+gHAY 4BTFRt7cA6jsirnKCCBmWe8j+QCx7QqT+ayhwGm0Enm8TcsuUlNmWxd9TCGf6956HIyq 1Hxq4UNQZL6cBa2Q22ufMGXIrYFFXtfS+nIEDJ+z1vDME/KSjzpLwa24LCaec2chgXcn 58rB1OJ+7NyCV4fkuATefSxsQk9MO3WbLE5vLhWAi5c5iNYm7zT7N+7YAs2EsnrhEzNo vWK/H12p0LxzbjLT1Bovt6lGQY34R6rhtV1Ov5rpWzXCLzGS5rLnVE4UAhK7dtPEg3G8 GmBQ== X-Gm-Message-State: AO0yUKVdgKnVcAHZK3pNRa+EywtSSCPZKbCJIAMDh8V/esbCVV2RqLzv 0Yx6FLYTK1DQIkKnM3QKfJH6 X-Google-Smtp-Source: AK7set/Qh8KRHmicnD4tRAyc/pFokfEegtVbSd77t9m9L68vrsXD4g0DQ2fUN6Lv5gvmKkJ4nUXelw== X-Received: by 2002:a05:6a20:bc98:b0:d0:76e3:16e5 with SMTP id fx24-20020a056a20bc9800b000d076e316e5mr8210613pzb.2.1678421333832; Thu, 09 Mar 2023 20:08:53 -0800 (PST) Received: from localhost.localdomain ([27.111.75.67]) by smtp.gmail.com with ESMTPSA id y26-20020aa7855a000000b0058d92d6e4ddsm361846pfn.5.2023.03.09.20.08.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Mar 2023 20:08:52 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v3 05/19] PCI: qcom: Use lower case for hex Date: Fri, 10 Mar 2023 09:38:02 +0530 Message-Id: <20230310040816.22094-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> References: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org To maintain uniformity, let's use lower case for representing hexadecimal numbers. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 926a531fda3a..4179ac973147 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -39,17 +39,17 @@ #define PARF_PCS_DEEMPH 0x34 #define PARF_PCS_SWING 0x38 #define PARF_PHY_CTRL 0x40 -#define PARF_PHY_REFCLK 0x4C +#define PARF_PHY_REFCLK 0x4c #define PARF_CONFIG_BITS 0x50 #define PARF_DBI_BASE_ADDR 0x168 -#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x16C /* Register offset specific to IP ver 2.3.3 */ +#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x16c /* Register offset specific to IP ver 2.3.3 */ #define PARF_MHI_CLOCK_RESET_CTRL 0x174 #define PARF_AXI_MSTR_WR_ADDR_HALT 0x178 -#define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8 -#define PARF_Q2A_FLUSH 0x1AC -#define PARF_LTSSM 0x1B0 +#define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8 +#define PARF_Q2A_FLUSH 0x1ac +#define PARF_LTSSM 0x1b0 #define PARF_SID_OFFSET 0x234 -#define PARF_BDF_TRANSLATE_CFG 0x24C +#define PARF_BDF_TRANSLATE_CFG 0x24c #define PARF_SLV_ADDR_SPACE_SIZE 0x358 #define PARF_DEVICE_TYPE 0x1000 #define PARF_BDF_TO_SID_TABLE_N 0x2000 @@ -60,7 +60,7 @@ /* DBI registers */ #define AXI_MSTR_RESP_COMP_CTRL0 0x818 #define AXI_MSTR_RESP_COMP_CTRL1 0x81c -#define MISC_CONTROL_1_REG 0x8BC +#define MISC_CONTROL_1_REG 0x8bc /* PARF_SYS_CTRL register fields */ #define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN BIT(29) -- 2.25.1