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Thu, 9 Mar 2023 21:18:54 -0800 Date: Thu, 9 Mar 2023 21:18:53 -0800 From: Nicolin Chen To: Jason Gunthorpe CC: Shameerali Kolothum Thodi , Jean-Philippe Brucker , "robin.murphy@arm.com" , "will@kernel.org" , "eric.auger@redhat.com" , "kevin.tian@intel.com" , "baolu.lu@linux.intel.com" , "joro@8bytes.org" , "linux-arm-kernel@lists.infradead.org" , "iommu@lists.linux.dev" , "linux-kernel@vger.kernel.org" , "yi.l.liu@intel.com" Subject: Re: [PATCH v1 02/14] iommufd: Add nesting related data structures for ARM SMMUv3 Message-ID: References: <364cfbe5b228ab178093db2de13fa3accf7a6120.1678348754.git.nicolinc@nvidia.com> <20230309134217.GA1673607@myrica> <213a05ef06944a55a148995053b187f8@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT079:EE_|PH8PR12MB8605:EE_ X-MS-Office365-Filtering-Correlation-Id: 8df17e05-b8ca-42f7-359b-08db2126f2bb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Mar 2023 05:18:56.6480 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8df17e05-b8ca-42f7-359b-08db2126f2bb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT079.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB8605 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Mar 09, 2023 at 11:40:16AM -0400, Jason Gunthorpe wrote: > On Thu, Mar 09, 2023 at 03:26:12PM +0000, Shameerali Kolothum Thodi wrote: > > > On platforms that supports BTM [1], we may need the VMID allocated by KVM. > > But again getting that from user pace doesn't look safe. I have attempted to revise > > the earlier RFC to pin and use the KVM VMID from SMMUv3 here[2]. > > Gurk > > > " In the new design we can require from the start that creating a nesting IOMMU > > container through /dev/iommu *must* come with a KVM context, that way > > we're sure to reuse the existing VMID. " > > I've been dreading this but yes I execpt we will eventually need to > connect kvm and iommufd together. The iommu driver can receive a kvm > pointer as part of the alloc domain operation to do any setups like > this. > > If there is no KVM it should either fail to setup the domain or setup > a domain disconnected from KVM. > > If IOMMU HW and KVM HW are using the same ID number space then > arguably the two kernel drivers need to use a shared ID allocator in > the arch, regardless of what iommufd/etc does. Using KVM should not be > mandatory for iommufd. > > For ARM cases where there is no shared VMID space with KVM, the ARM > VMID should be somehow assigned to the iommfd_ctx itself and the alloc > domain op should receive it from there. > > Nicolin, that seems to be missing in this series? I'm not entirely > sure how to elegantly code it :\ Yea, it's missing. The VMID thing is supposed to be a sneak peek of my next VCMDQ solution. Now it seems that BTM needs this too. Remember that my previous VCMDQ series had a big complication to share VMID across the passthrough devices in the same VM? During that patch review, we concluded that IOMMUFD would simply align VMIDs using a unified ctx ID or so, IIRC. Thanks Nic