Message-ID: <10f872cc-b502-61ca-aefa-3047a9dfe5cd@arinc9.com>
Date:   Fri, 10 Mar 2023 13:21:42 +0300
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Subject: Re: [PATCH v3 net 2/2] net: dsa: mt7530: set PLL frequency and trgmii
 only when trgmii is used
To:     Sean Wang <sean.wang@mediatek.com>,
        Landen Chao <Landen.Chao@mediatek.com>,
        DENG Qingfang <dqfext@gmail.com>, Andrew Lunn <andrew@lunn.ch>,
        Florian Fainelli <f.fainelli@gmail.com>,
        Vladimir Oltean <olteanv@gmail.com>,
        "David S. Miller" <davem@davemloft.net>,
        Eric Dumazet <edumazet@google.com>,
        Jakub Kicinski <kuba@kernel.org>,
        Paolo Abeni <pabeni@redhat.com>,
        Matthias Brugger <matthias.bgg@gmail.com>,
        AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@collabora.com>,
        =?UTF-8?Q?Ren=c3=a9_van_Dorst?= <opensource@vdorst.com>,
        Russell King <rmk+kernel@armlinux.org.uk>
Cc:     netdev@vger.kernel.org, erkin.bozoglu@xeront.com,
        linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-mediatek@lists.infradead.org
References: <20230310073338.5836-1-arinc.unal@arinc9.com>
 <20230310073338.5836-2-arinc.unal@arinc9.com>
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From:   =?UTF-8?B?QXLEsW7DpyDDnE5BTA==?= <arinc.unal@arinc9.com>
In-Reply-To: <20230310073338.5836-2-arinc.unal@arinc9.com>
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On 10.03.2023 10:33, arinc9.unal@gmail.com wrote:
> From: Arınç ÜNAL <arinc.unal@arinc9.com>
> 
> As my testing on the MCM MT7530 switch on MT7621 SoC shows, setting the PLL
> frequency does not affect MII modes other than trgmii on port 5 and port 6.
> So the assumption is that the operation here called "setting the PLL
> frequency" actually sets the frequency of the TRGMII TX clock.
> 
> Make it so that it and the rest of the trgmii setup run only when the
> trgmii mode is used.
> 
> Tested rgmii and trgmii modes of port 6 on MCM MT7530 on MT7621AT Unielec
> U7621-06 and standalone MT7530 on MT7623NI Bananapi BPI-R2.
> 
> Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 switch")
> Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com>
> Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
> ---
>   drivers/net/dsa/mt7530.c | 62 ++++++++++++++++++++--------------------
>   1 file changed, 31 insertions(+), 31 deletions(-)
> 
> diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c
> index b1a79460df0e..c2d81b7a429d 100644
> --- a/drivers/net/dsa/mt7530.c
> +++ b/drivers/net/dsa/mt7530.c
> @@ -430,8 +430,6 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
>   	switch (interface) {
>   	case PHY_INTERFACE_MODE_RGMII:
>   		trgint = 0;
> -		/* PLL frequency: 125MHz */
> -		ncpo1 = 0x0c80;
>   		break;
>   	case PHY_INTERFACE_MODE_TRGMII:
>   		trgint = 1;
> @@ -462,38 +460,40 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
>   	mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
>   		   P6_INTF_MODE(trgint));
>   
> -	/* Lower Tx Driving for TRGMII path */
> -	for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
> -		mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
> -			     TD_DM_DRVP(8) | TD_DM_DRVN(8));
> -
> -	/* Disable MT7530 core and TRGMII Tx clocks */
> -	core_clear(priv, CORE_TRGMII_GSW_CLK_CG,
> -		   REG_GSWCK_EN | REG_TRGMIICK_EN);
> -
> -	/* Setup the MT7530 TRGMII Tx Clock */
> -	core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
> -	core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
> -	core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
> -	core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
> -	core_write(priv, CORE_PLL_GROUP4,
> -		   RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN |
> -		   RG_SYSPLL_BIAS_LPF_EN);
> -	core_write(priv, CORE_PLL_GROUP2,
> -		   RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
> -		   RG_SYSPLL_POSDIV(1));
> -	core_write(priv, CORE_PLL_GROUP7,
> -		   RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |
> -		   RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
> -
> -	/* Enable MT7530 core and TRGMII Tx clocks */
> -	core_set(priv, CORE_TRGMII_GSW_CLK_CG,
> -		 REG_GSWCK_EN | REG_TRGMIICK_EN);
> -
> -	if (!trgint)
> +	if (trgint) {
> +		/* Lower Tx Driving for TRGMII path */
> +		for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
> +			mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
> +				     TD_DM_DRVP(8) | TD_DM_DRVN(8));
> +
> +		/* Disable MT7530 core and TRGMII Tx clocks */
> +		core_clear(priv, CORE_TRGMII_GSW_CLK_CG,
> +			   REG_GSWCK_EN | REG_TRGMIICK_EN);
> +
> +		/* Setup the MT7530 TRGMII Tx Clock */
> +		core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
> +		core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
> +		core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
> +		core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
> +		core_write(priv, CORE_PLL_GROUP4,
> +			   RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN |
> +			   RG_SYSPLL_BIAS_LPF_EN);
> +		core_write(priv, CORE_PLL_GROUP2,
> +			   RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
> +			   RG_SYSPLL_POSDIV(1));
> +		core_write(priv, CORE_PLL_GROUP7,
> +			   RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |
> +			   RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
> +
> +		/* Enable MT7530 core and TRGMII Tx clocks */
> +		core_set(priv, CORE_TRGMII_GSW_CLK_CG,
> +			 REG_GSWCK_EN | REG_TRGMIICK_EN);
> +	} else {
>   		for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
>   			mt7530_rmw(priv, MT7530_TRGMII_RD(i),
>   				   RD_TAP_MASK, RD_TAP(16));

This code runs if the phy mode is not trgmii. Other than trgmii, only 
the rgmii mode is supported on the hardware so this runs when the rgmii 
mode is used on port 6.

I've tested the rgmii mode on MCM and standalone MT7530 without running 
this code and it works fine. Close to gigabit download/upload speed and 
no packet loss. I don't understand why the TRGMII RX registers are 
modified when the trgmii mode is not used at all.

I don't suppose anyone from MediaTek would clarify, so this presumably 
dead code will remain.

Arınç