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Sat, 11 Mar 2023 04:38:05 -0800 Date: Sat, 11 Mar 2023 04:38:03 -0800 From: Nicolin Chen To: Robin Murphy CC: , , , , , , , , , , Subject: Re: [PATCH v1 14/14] iommu/arm-smmu-v3: Add arm_smmu_cache_invalidate_user Message-ID: References: <1467e666-1b6c-c285-3f79-f8e8b088718b@arm.com> <92fdb06f-e5b1-8534-fb0e-ad47b5be9e1d@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <92fdb06f-e5b1-8534-fb0e-ad47b5be9e1d@arm.com> X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF000108E9:EE_|PH8PR12MB7302:EE_ X-MS-Office365-Filtering-Correlation-Id: 8a89348f-c3d1-47f1-31b1-08db222d7754 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ZjXp/sRiwfUKdWTcMhKKUvfA6gT71l+LMIXnivxE1Czl+k4E+1iTVKd2011Dpkp4qQEgIbNcmC9Ohrsm7BAIfaKn84rFlDfGodfI4RwKPzfJsjaUDlvvpkwYpwK0URNKLWXfihEZguL/SmY2BjekC8ccLOfYT5Pl3pEZHaqf5vcIIiYXfpvwkoWxFiiA8dNXfyR0PmOPZgHiWntTl4THAbXd2kRBAFTF4JcIE5jDZFtkH/vlxwqrVFAR7Ovfa5EzU0n3C+J4GLvk+2jd3N/tupScRq18yQ57tB9WnmeO+QprFiF/XgywDOTcDTME459vSyQX3BdoVwEB7vIY9KqFib6LjKSkDJhqONpXRgS/rtrMyMBlSKdaQjf9VcdDh0FOxArnrGtZ6ZQQuJWQyVy+jY/KZbJ9HT3j9ddFvlrkKja+k6eYLXEPJTLU5GM+fgIgH8naCvxcvQeB29+5mbLvoy3XgVLBHOazJJx28xIxUVP1WIOxx6dsiC9uUuF6KFKuhenztQQLB0ABZXn+VYfR3uT4+mL5Hq7mRiJ+aPhAjQluO2/OAF27h30mTc8epY2XFwuZUxn7Ov0xQ/jHyOQ8pr+R4gyurIMRRDGUEUfX4xl0SbABfHSev/MHBBRW35MwdHIaVVeUCcp/JokVsxEKlPyBBC8wXYfUKSsZGo5d1PcJ9ZimkWRw3DloefSRTLvudCMVFuQalBurSwMzbv38/RnXtoMipHlpQ7teIFN8hFhHDFrB5WWUkyHoSVNId1QD X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230025)(4636009)(346002)(376002)(136003)(396003)(39860400002)(451199018)(36840700001)(40470700004)(46966006)(70586007)(70206006)(4326008)(36860700001)(6916009)(83380400001)(47076005)(426003)(33716001)(82740400003)(7636003)(336012)(41300700001)(66899018)(82310400005)(316002)(8936002)(186003)(9686003)(54906003)(26005)(356005)(8676002)(40480700001)(55016003)(478600001)(7416002)(40460700003)(2906002)(86362001)(5660300002);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Mar 2023 12:38:07.1904 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8a89348f-c3d1-47f1-31b1-08db222d7754 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000108E9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7302 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Mar 10, 2023 at 05:53:46PM +0000, Robin Murphy wrote: > > > > + case CMDQ_OP_TLBI_NH_VA: > > > > + cmd.tlbi.asid = inv_info->asid; > > > > + fallthrough; > > > > + case CMDQ_OP_TLBI_NH_VAA: > > > > + if (!granule_size || !(granule_size & smmu->pgsize_bitmap) || > > > > > > Non-range invalidations with TG=0 are perfectly legal, and should not be > > > ignored. > > > > I assume that you are talking about the pgsize_bitmap check. > > > > QEMU embeds a !tg case into the granule_size [1]. So it might > > not be straightforward to cover that case. Let me see how to > > untangle different cases and handle them accordingly. > > Oh, double-checking patch #2, that might be me misunderstanding the > interface. I hadn't realised that the UAPI was apparently modelled on > arm_smmu_tlb_inv_range_asid() rather than actual SMMU commands :) Yea. In fact, most of the invalidation info in QEMU was packed for the previously defined general cache invalidation structure, and the range invalidation part is still not quite independent. > I really think UAPI should reflect the hardware and encode TG and TTL > directly. Especially since there's technically a flaw in the current > driver where we assume TTL in cases where it isn't actually known, thus > may potentially fail to invalidate level 2 block entries when removing a > level 1 table, since io-pgtable passes the level 3 granule in that case. Do you mean something like hw_info forwarding pgsize_bitmap/tg to the guest? Or the other direction? > When range invalidation came along, the distinction between "all leaves > are definitely at the last level" and "use last-level granularity to > make sure everything at at any level is hit" started to matter, but the > interface never caught up. It hasn't seemed desperately urgent to fix > (who does 1GB+ unmaps outside of VFIO teardown anyway?), but we must > definitely not bake the same mistake into user ABI. > > Of course, there might then be cases where we need to transform > non-range commands into range commands for the sake of workarounds, but > that's our own problem to deal with. Noted it down. > > > What about NSNH_ALL? That still needs to invalidate all the S1 context > > > that the guest *thinks* it's invalidating. > > > > NSNH_ALL is translated to NH_ALL at the guest level. But maybe > > it should have been done here instead. > > Yes. It seems the worst of both worlds to have an interface which takes > raw opcodes rather than an enum of supported commands, but still > requires userspace to know which opcodes are supported and which ones > don't work as expected even though they are entirely reasonable to use > in the context of the stage-1-only SMMU being emulated. Maybe a list of supported TLBI commands via the hw_info uAPI? Thanks Nic