Message-ID: <5441450e-be39-1033-b3d5-c3eb10950d34@linaro.org>
Date:   Mon, 13 Mar 2023 09:32:07 +0100
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Subject: Re: [PATCH] arm64: dts: qcom: qdu1000: Add
 LLCC/system-cache-controller node
To:     Komal Bajaj <quic_kbajaj@quicinc.com>,
        Andy Gross <agross@kernel.org>,
        Bjorn Andersson <andersson@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc:     linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org
References: <20230313071757.31533-1-quic_kbajaj@quicinc.com>
Content-Language: en-US
From:   Konrad Dybcio <konrad.dybcio@linaro.org>
In-Reply-To: <20230313071757.31533-1-quic_kbajaj@quicinc.com>
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On 13.03.2023 08:17, Komal Bajaj wrote:
> Add a DT node for Last level cache (aka. system cache) controller
> which provides control over the last level cache present on QDU1000
> and QRU1000 SoCs.
> 
> Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/qdu1000.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
> index 801f090335a3..a4816a862344 100644
> --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
> @@ -1321,6 +1321,16 @@ gem_noc: interconnect@19100000 {
>  			qcom,bcm-voters = <&apps_bcm_voter>;
>  			#interconnect-cells = <2>;
>  		};
> +
> +		system-cache-controller@19200000 {
> +			compatible = "qcom,qdu1000-llcc";
> +			reg = <0 0x19200000 0 0xd80000>,
> +			      <0 0x1a200000 0 0x80000>,
> +			      <0 0x221c8128 0 0x4>;
> +			reg-names = "llcc_base", "llcc_broadcast_base", "multi_channel_register";
Please turn this into a vertical list, like you did with reg

> +			multi-ch-bit-off = <24 2>;
driver-specific properties generally go after the generic ones,
so swap this one with interrupts

Konrad
> +			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
> +		};
>  	};
>  
>  	arch_timer: timer {