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Date:   Mon, 13 Mar 2023 10:37:23 -0700
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Subject: Re: [PATCH] mips: bmips: BCM6358: disable arch_sync_dma_for_cpu_all()
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To:     =?UTF-8?Q?=c3=81lvaro_Fern=c3=a1ndez_Rojas?= <noltari@gmail.com>,
        Florian Fainelli <f.fainelli@gmail.com>
Cc:     William Zhang <william.zhang@broadcom.com>,
        Jonas Gorski <jonas.gorski@gmail.com>,
        bcm-kernel-feedback-list@broadcom.com, tsbogend@alpha.franken.de,
        linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org
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From:   Florian Fainelli <f.fainelli@gmail.com>
In-Reply-To: <CAKR-sGfL5_VU9uxJHGyZ-bj2P_7R6+OOfWs6Yf-ihcCF8bD2MA@mail.gmail.com>
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On 3/12/23 11:50, Álvaro Fernández Rojas wrote:
> Hi Florian,
> 
> I tried what you suggested but it stil panics on EHCI:
> 
> [    0.000000] Linux version 5.15.98 (noltari@atlantis)
> (mips-openwrt-linux-musl-gcc (OpenWrt GCC 12.2.0 r22187+1-19817fa3f5)
> 12.2.0, GNU ld (GNU Binutils) 2.40.0) #0 SMP Sun Mar 12 18:23:28 2023
> [    0.000000] bmips_cpu_setup: read_c0_brcm_config_0() = 0xe30e1006
> [    0.000000] bmips_cpu_setup: cbr + BMIPS_RAC_CONFIG = 0x3c1b8041
> [    0.000000] CPU0 revision is: 0002a010 (Broadcom BMIPS4350)
> 
> It looks like bit 29 is set so RAC should be present.
> And RAC_I seems to be set, but not RAC_D...
> 
> BTW, this is what I added to bmips_cpu_setup:
> 
> case CPU_BMIPS4350:
> cfg = read_c0_brcm_config_0();
> pr_info("bmips_cpu_setup: read_c0_brcm_config_0() = 0x%x\n", cfg);
> 
> cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
> pr_info("bmips_cpu_setup: cbr + BMIPS_RAC_CONFIG = 0x%x\n", cfg);
> __raw_writel(cfg | BIT(0) | BIT(1), cbr + BMIPS_RAC_CONFIG);
> __raw_readl(cbr + BMIPS_RAC_CONFIG);
> break;

Thanks for running those experiments, I cannot explain what you are 
seeing, so there must be some sort of erratum applicable to the 
BMIPS4380 revision used on the 6358 somehow...

If you can make the suggested change to use negative logic in order to 
disable the RAC flushing, that would work for me, also maybe add a 
Fixes: tag so it gets backported to stable trees?

Thanks!
-- 
Florian