Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01EA4C61DA4 for ; Mon, 13 Mar 2023 21:01:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230502AbjCMVBh (ORCPT ); Mon, 13 Mar 2023 17:01:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49458 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230375AbjCMVBE (ORCPT ); Mon, 13 Mar 2023 17:01:04 -0400 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 95012848CD; Mon, 13 Mar 2023 14:00:34 -0700 (PDT) Received: by mail-ed1-x530.google.com with SMTP id ek18so22899894edb.6; Mon, 13 Mar 2023 14:00:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1678741232; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yAgVEaQ3wTWSM/roB3rZ4d22w+naU3QZ4J68IrDFTUw=; b=IalN9Q8RaXhjHjxH3l9HGeNjsyB3xTYsslGPKTz8tChbt/Iwdvm+yvjo0LZ8FH+mkZ /RPwdd8qZpyy77bbX3v2FxsP7Eqo2KVsBHDvx5E71n2i7nsQ7NCiIPkF3QvQGgcVn4xW wpnUR6TsFlPxV6ZDTT3oCcoM0UPzMoSK9CcNijBmmQowD6qkajRqmY5KF5pVa2B0L5XC 2mBbap3IF2h8owmV8DQnPkeUWIjuYQczHNP5IS11/6FDOFmG8XzDDJ4nDWMAaO4kP66V AhCMQweebRzKoBC+vzrrc2BVZ5Ske7bMVmouggePpR26a+qFiSLFTZc09RQVcjscoLOL ORrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678741232; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yAgVEaQ3wTWSM/roB3rZ4d22w+naU3QZ4J68IrDFTUw=; b=jQRou4rWNVHQuHlpCh8POWjUxKL4GmFnB57kkQh31HCWqAnqQusQuSlGNc7MKxViUZ BV2fOmCoiRFUq5HqT9BhyQsxjNKVEo+wC3SS1/jfTKnZFCi1CO92sG5aIC12JS161JLc cEw0u4yh4XuDqJ9uG4iyR60qMAm6Dv2mj5Zbfgi7Kd4FUDmb9oAu6OvMkg45C0CcsFhB XQed+3qBKc5/C3w9piUsdoReds6RgNYNkO8e6ko3J0bjgRPFtaWeinBrKncAE8YUPr0z FqRuDbaISnB/f1nkXwbp0Z6SJn1FS72UjICr+aXvHuaKeLlMvIOT67QTyuhmybyg7A+Y EA/w== X-Gm-Message-State: AO0yUKXCqV7WUBi1ek+dj28NDGQhffYFmLDujI8E2TJqETmbGpuo2YiO Pqwgz6pk2AiaWR35DdcXp7I= X-Google-Smtp-Source: AK7set+G713ElsBQl+Y9N92iqgiMaNOa80KkfENVNuNDxxOqv9NftZuA9TMy3fMZJU5ZhXHZOLxb/Q== X-Received: by 2002:a17:906:b007:b0:8aa:c038:974c with SMTP id v7-20020a170906b00700b008aac038974cmr36455676ejy.54.1678741232102; Mon, 13 Mar 2023 14:00:32 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id j11-20020a170906830b00b008ee5356801dsm219853ejx.187.2023.03.13.14.00.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Mar 2023 14:00:31 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= , Sergio Paracuellos , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v2 16/21] dt-bindings: pinctrl: mediatek: fix pinmux header location Date: Mon, 13 Mar 2023 23:59:16 +0300 Message-Id: <20230313205921.35342-17-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230313205921.35342-1-arinc.unal@arinc9.com> References: <20230313205921.35342-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Arınç ÜNAL Fix the location of the pinmux header files mentioned on the schemas. Signed-off-by: Arınç ÜNAL --- .../devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml | 2 +- .../devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml | 2 +- .../devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml index 5e80621800a9..3b3d59140073 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml @@ -90,7 +90,7 @@ patternProperties: description: Integer array, represents gpio pin number and mux setting. Supported pin number and mux varies for different SoCs, and are - defined as macros in -pinfunc.h directly. + defined as macros in dt-bindings/pinctrl/-pinfunc.h directly. bias-disable: true diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml index 1d038f6f8971..e5e7143674b5 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml @@ -131,7 +131,7 @@ patternProperties: description: Integer array, represents gpio pin number and mux setting. Supported pin number and mux varies for different SoCs, and are - defined as macros in boot/dts/-pinfunc.h directly. + defined as macros in dt-bindings/pinctrl/-pinfunc.h directly. bias-disable: true diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml index 51b3d1247614..028146fb173f 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml @@ -88,8 +88,8 @@ patternProperties: description: Integer array, represents gpio pin number and mux setting. Supported pin number and mux varies for different SoCs, and are - defined as macros in dt-bindings/pinctrl/mediatek,-pinfunc.h - directly. + defined as macros in dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h + directly, for this SoC. drive-strength: enum: [2, 4, 6, 8, 10, 12, 14, 16] -- 2.37.2