From:   Peng Fan <peng.fan@nxp.com>
To:     Adam Ford <aford173@gmail.com>,
        "linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>
CC:     "l.stach@pengutronix.de" <l.stach@pengutronix.de>,
        Abel Vesa <abelvesa@kernel.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Shawn Guo <shawnguo@kernel.org>,
        Sascha Hauer <s.hauer@pengutronix.de>,
        Pengutronix Kernel Team <kernel@pengutronix.de>,
        Fabio Estevam <festevam@gmail.com>,
        dl-linux-imx <linux-imx@nxp.com>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: RE: [RFC] clk: imx: Let IMX8MN_CLK_DISP_PIXEL set parent rate
Thread-Topic: [RFC] clk: imx: Let IMX8MN_CLK_DISP_PIXEL set parent rate
Thread-Index: AQHZVh755FFcwu4ibEmsRm2CLElfAK75sXLA
Date:   Tue, 14 Mar 2023 04:39:24 +0000
Message-ID: <DU0PR04MB9417C49457C9E60898E6A92188BE9@DU0PR04MB9417.eurprd04.prod.outlook.com>
References: <20230314024449.50151-1-aford173@gmail.com>
In-Reply-To: <20230314024449.50151-1-aford173@gmail.com>
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> Subject: [RFC] clk: imx: Let IMX8MN_CLK_DISP_PIXEL set parent rate
>=20
> By default the display pixel clock needs to be evenly divide down from
> 594MHz which rules out a significant number of resolution and refresh rat=
es.
> The current clock tree looks something like:
>=20
>  video_pll                594000000
>   video_pll_bypass        594000000
>    video_pll_out          594000000
>     disp_pixel            148500000
>      disp_pixel_clk       148500000
>=20
> To enable CLK_SET_RATE_PARENT on disp_pixel, a helper function needs to
> be added called imx8m_clk_hw_composite_flags which can pass the
> additional flag to the clock controller. Letting disp_pixel set video_pll=
_out
> rate should actually lower the clock rates of video_pll_bypass and video_=
pll
> as well, since those clocks are already configured to enable
> CLK_SET_RATE_PARENT.
>=20
> Signed-off-by: Adam Ford <aford173@gmail.com>
> ---
>=20
> This is an RFC, because even with this patch, the video_pll_out clock doe=
s
> not drop to 148500000 like I would expect.  The video_pll clock is a
> fractional pll, so it should be able to generate a significant number of
> optional clock frequencies to facilitate video.
[Peng Fan]=20

Have you ever tried to directly set video pll out clk to the freq that you =
wanna?

Regards,
Peng.

>=20
> diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
> index af256ade554f..a116cc40d7d0 100644
> --- a/drivers/clk/imx/clk-imx8mn.c
> +++ b/drivers/clk/imx/clk-imx8mn.c
> @@ -470,7 +470,7 @@ static int imx8mn_clocks_probe(struct
> platform_device *pdev)
>  	hws[IMX8MN_CLK_DRAM_ALT] =3D
> imx8m_clk_hw_fw_managed_composite("dram_alt",
> imx8mn_dram_alt_sels, base + 0xa000);
>  	hws[IMX8MN_CLK_DRAM_APB] =3D
> imx8m_clk_hw_fw_managed_composite_critical("dram_apb",
> imx8mn_dram_apb_sels, base + 0xa080);
>=20
> -	hws[IMX8MN_CLK_DISP_PIXEL] =3D
> imx8m_clk_hw_composite("disp_pixel", imx8mn_disp_pixel_sels, base +
> 0xa500);
> +	hws[IMX8MN_CLK_DISP_PIXEL] =3D
> +imx8m_clk_hw_composite_flags("disp_pixel", imx8mn_disp_pixel_sels,
> base
> ++ 0xa500, CLK_SET_RATE_PARENT);
>  	hws[IMX8MN_CLK_SAI2] =3D imx8m_clk_hw_composite("sai2",
> imx8mn_sai2_sels, base + 0xa600);
>  	hws[IMX8MN_CLK_SAI3] =3D imx8m_clk_hw_composite("sai3",
> imx8mn_sai3_sels, base + 0xa680);
>  	hws[IMX8MN_CLK_SAI5] =3D imx8m_clk_hw_composite("sai5",
> imx8mn_sai5_sels, base + 0xa780); diff --git a/drivers/clk/imx/clk.h
> b/drivers/clk/imx/clk.h index 689b3ad927c0..9977b512845b 100644
> --- a/drivers/clk/imx/clk.h
> +++ b/drivers/clk/imx/clk.h
> @@ -414,6 +414,10 @@ struct clk_hw *__imx8m_clk_hw_composite(const
> char *name,
>  	_imx8m_clk_hw_composite(name, parent_names, reg, \
>  			0, IMX_COMPOSITE_CLK_FLAGS_DEFAULT)
>=20
> +#define imx8m_clk_hw_composite_flags(name, parent_names, reg, flags)
> \
> +	_imx8m_clk_hw_composite(name, parent_names, reg, \
> +			0, IMX_COMPOSITE_CLK_FLAGS_DEFAULT |  flags)
> +
>  #define imx8m_clk_hw_composite_critical(name, parent_names, reg) \
>  	_imx8m_clk_hw_composite(name, parent_names, reg, \
>  			0, IMX_COMPOSITE_CLK_FLAGS_CRITICAL)
> --
> 2.37.2