Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED4F2C6FD1F for ; Tue, 14 Mar 2023 05:03:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229701AbjCNFD3 convert rfc822-to-8bit (ORCPT ); Tue, 14 Mar 2023 01:03:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33884 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229486AbjCNFD1 (ORCPT ); Tue, 14 Mar 2023 01:03:27 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B390126AE for ; Mon, 13 Mar 2023 22:03:25 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 8F0A024DC31; Tue, 14 Mar 2023 13:03:23 +0800 (CST) Received: from EXMBX066.cuchost.com (172.16.7.66) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 14 Mar 2023 13:03:23 +0800 Received: from jsia-virtual-machine.localdomain (202.188.176.82) by EXMBX066.cuchost.com (172.16.6.66) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 14 Mar 2023 13:03:20 +0800 From: Sia Jee Heng To: , , CC: , , , , Subject: [PATCH v6 0/4] RISC-V Hibernation Support Date: Tue, 14 Mar 2023 13:03:12 +0800 Message-ID: <20230314050316.31701-1-jeeheng.sia@starfivetech.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [202.188.176.82] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX066.cuchost.com (172.16.6.66) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: 8BIT Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This series adds RISC-V Hibernation/suspend to disk support. Low level Arch functions were created to support hibernation. swsusp_arch_suspend() relies code from __cpu_suspend_enter() to write cpu state onto the stack, then calling swsusp_save() to save the memory image. Arch specific hibernation header is implemented and is utilized by the arch_hibernation_header_restore() and arch_hibernation_header_save() functions. The arch specific hibernation header consists of satp, hartid, and the cpu_resume address. The kernel built version is also need to be saved into the hibernation image header to making sure only the same kernel is restore when resume. swsusp_arch_resume() creates a temporary page table that covering only the linear map. It copies the restore code to a 'safe' page, then start to restore the memory image. Once completed, it restores the original kernel's page table. It then calls into __hibernate_cpu_resume() to restore the CPU context. Finally, it follows the normal hibernation path back to the hibernation core. To enable hibernation/suspend to disk into RISCV, the below config need to be enabled: - CONFIG_ARCH_HIBERNATION_HEADER - CONFIG_ARCH_HIBERNATION_POSSIBLE At high-level, this series includes the following changes: 1) Change suspend_save_csrs() and suspend_restore_csrs() to public function as these functions are common to suspend/hibernation. (patch 1) 2) Refactor the common code in the __cpu_resume_enter() function and __hibernate_cpu_resume() function. The common code are used by hibernation and suspend. (patch 2) 3) Enhance kernel_page_present() function to support huge page. (patch 3) 4) Add arch/riscv low level functions to support hibernation/suspend to disk. (patch 4) The above patches are based on kernel v6.3-rc2 and are tested on StarFive VF2 SBC board and Qemu. ACPI platform mode is not supported in this series. Changes since v5: - Rebased to kernel v6.3-rc2 - Removed extra line at the commit msg - Added comment to describe the reason to map the kernel address Changes since v4: - Rebased to kernel v6.3-rc1 - Resolved typo(s) - Removed unnecessary helper function - Removed unnecessary "addr" local variable - Removed typecast of 'int' - Used def_bool HIBERNATION - Used "mv a0, zero" instead of "add a0, zero, zero" - Make linear region as executable and writable when restoring the image Changes since v3: - Rebased to kernel v6.2 - Temporary page table code refactoring by reference to ARM64 - Resolved typo(s) and grammars - Resolved documentation errors - Resolved clang build issue - Removed unnecessary comments - Used kzalloc instead of kcalloc Changes since v2: - Rebased to kernel v6.2-rc5 - Refactor the common code used by hibernation and suspend - Create copy_page macro - Solved other comments from Andrew and Conor Changes since v1: - Rebased to kernel v6.2-rc3 - Fixed bot's compilation error Sia Jee Heng (4): RISC-V: Change suspend_save_csrs and suspend_restore_csrs to public function RISC-V: Factor out common code of __cpu_resume_enter() RISC-V: mm: Enable huge page support to kernel_page_present() function RISC-V: Add arch functions to support hibernation/suspend-to-disk arch/riscv/Kconfig | 6 + arch/riscv/include/asm/assembler.h | 82 ++++++ arch/riscv/include/asm/suspend.h | 22 ++ arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/asm-offsets.c | 5 + arch/riscv/kernel/hibernate-asm.S | 77 ++++++ arch/riscv/kernel/hibernate.c | 427 +++++++++++++++++++++++++++++ arch/riscv/kernel/suspend.c | 4 +- arch/riscv/kernel/suspend_entry.S | 34 +-- arch/riscv/mm/pageattr.c | 8 + 10 files changed, 633 insertions(+), 33 deletions(-) create mode 100644 arch/riscv/include/asm/assembler.h create mode 100644 arch/riscv/kernel/hibernate-asm.S create mode 100644 arch/riscv/kernel/hibernate.c base-commit: fc89d7fb499b0162e081f434d45e8d1b47e82ece -- 2.34.1