Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 674B6C74A44 for ; Tue, 14 Mar 2023 06:26:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229801AbjCNG0Y (ORCPT ); Tue, 14 Mar 2023 02:26:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36682 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229616AbjCNG0W (ORCPT ); Tue, 14 Mar 2023 02:26:22 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2C72B8B324; Mon, 13 Mar 2023 23:26:19 -0700 (PDT) Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32E4tnA1028638; Tue, 14 Mar 2023 06:26:13 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=message-id : date : mime-version : subject : to : cc : references : from : in-reply-to : content-type : content-transfer-encoding; s=qcppdkim1; bh=MCUt6f1r/DmukcSQ1l+aE5+TMMUE1G6sDmdU3o/lCls=; b=iDZ1bl1gLWzSgNZQI4yebY0oXOlfZ1HqJN/ZbBR9EFixtaP0JavbqZQlwkOuRnIxy4Ed 4JfPr+ZdFnYxinxMtYUWI0WpkIsUH1EVVojw7jekHYdCkrXnhIbaHWzWwmntgaM0Zt0Q Ur0XivCev98T15Id9Ou3beKx3b/EVnsxAPNJCXftdWhj0SqnP1+Z7MMe3/SkKfiz+CQP QrJHhnbWBySYBPammjcl+aNJJk9ZR10zsCCy8zdZ1Rl4d3ous3BUzSBkiXPp7KJqgtQW MCe9nHfZbQKKT8ZrUmEydYQ8vYKORY70qXlSJNqluuHA1KQZCZmxZhSiOATJ+WCyVYm9 Ug== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3paay3997d-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 14 Mar 2023 06:26:13 +0000 Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 32E6QCSr032054 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 14 Mar 2023 06:26:12 GMT Received: from [10.206.12.35] (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 13 Mar 2023 23:26:08 -0700 Message-ID: Date: Tue, 14 Mar 2023 11:55:59 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.7.0 Subject: Re: [PATCH v4 2/2] arm64: dts: qcom: add initial support for qcom sa8775p-ride To: Bartosz Golaszewski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , Jassi Brar , Rob Herring , Krzysztof Kozlowski CC: , , , Bartosz Golaszewski References: <20230214092713.211054-1-brgl@bgdev.pl> <20230214092713.211054-3-brgl@bgdev.pl> Content-Language: en-US From: Shazad Hussain In-Reply-To: <20230214092713.211054-3-brgl@bgdev.pl> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: oJHRbtmglxnu4XiVMEwNTExYutbZ-KKr X-Proofpoint-GUID: oJHRbtmglxnu4XiVMEwNTExYutbZ-KKr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-13_13,2023-03-14_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 mlxscore=0 mlxlogscore=999 malwarescore=0 adultscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 spamscore=0 impostorscore=0 priorityscore=1501 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2303140056 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2/14/2023 2:57 PM, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski > > This adds basic support for the Qualcomm sa8775p platform and the > reference board: sa8775p-ride. The dt files describe the basics of the > SoC and enable booting to shell. > > Signed-off-by: Bartosz Golaszewski > Reviewed-by: Konrad Dybcio > --- > arch/arm64/boot/dts/qcom/Makefile | 1 + > arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 47 ++ > arch/arm64/boot/dts/qcom/sa8775p.dtsi | 805 ++++++++++++++++++++++ > 3 files changed, 853 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/sa8775p-ride.dts > create mode 100644 arch/arm64/boot/dts/qcom/sa8775p.dtsi > > diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile > index 31aa54f0428c..b63cd1861e68 100644 > --- a/arch/arm64/boot/dts/qcom/Makefile > +++ b/arch/arm64/boot/dts/qcom/Makefile > @@ -75,6 +75,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb > dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb > dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb > dtb-$(CONFIG_ARCH_QCOM) += sa8540p-ride.dtb > +dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride.dtb > dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb > dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb > dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb > diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts > new file mode 100644 > index 000000000000..3adf7349f4e5 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts > @@ -0,0 +1,47 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Copyright (c) 2023, Linaro Limited > + */ > + > +/dts-v1/; > + > +#include "sa8775p.dtsi" > + > +/ { > + model = "Qualcomm SA8775P Ride"; > + compatible = "qcom,sa8775p-ride", "qcom,sa8775p"; > + > + aliases { > + serial0 = &uart10; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > +}; > + > +&qupv3_id_1 { > + status = "okay"; > +}; > + > +&sleep_clk { > + clock-frequency = <32764>; > +}; > + > +&tlmm { > + qup_uart10_default: qup-uart10-state { > + pins = "gpio46", "gpio47"; > + function = "qup1_se3"; > + }; > +}; Can we keep &tlmm at the end ? As this would be expanding. -Shazad > + > +&uart10 { > + compatible = "qcom,geni-debug-uart"; > + pinctrl-0 = <&qup_uart10_default>; > + pinctrl-names = "default"; > + status = "okay"; > +}; > + > +&xo_board_clk { > + clock-frequency = <38400000>; > +}; > diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > new file mode 100644 > index 000000000000..565c1376073e > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > @@ -0,0 +1,805 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Copyright (c) 2023, Linaro Limited > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > + > +/ { > + interrupt-parent = <&intc>; > + > + #address-cells = <2>; > + #size-cells = <2>; > + > + clocks { > + xo_board_clk: xo-board-clk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + }; > + > + sleep_clk: sleep-clk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + }; > + }; > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + CPU0: cpu@0 { > + device_type = "cpu"; > + compatible = "qcom,kryo"; > + reg = <0x0 0x0>; > + enable-method = "psci"; > + next-level-cache = <&L2_0>; > + L2_0: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + L3_0: l3-cache { > + compatible = "cache"; > + }; > + }; > + }; > + > + CPU1: cpu@100 { > + device_type = "cpu"; > + compatible = "qcom,kryo"; > + reg = <0x0 0x100>; > + enable-method = "psci"; > + next-level-cache = <&L2_1>; > + L2_1: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + }; > + }; > + > + CPU2: cpu@200 { > + device_type = "cpu"; > + compatible = "qcom,kryo"; > + reg = <0x0 0x200>; > + enable-method = "psci"; > + next-level-cache = <&L2_2>; > + L2_2: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + }; > + }; > + > + CPU3: cpu@300 { > + device_type = "cpu"; > + compatible = "qcom,kryo"; > + reg = <0x0 0x300>; > + enable-method = "psci"; > + next-level-cache = <&L2_3>; > + L2_3: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + }; > + }; > + > + CPU4: cpu@10000 { > + device_type = "cpu"; > + compatible = "qcom,kryo"; > + reg = <0x0 0x10000>; > + enable-method = "psci"; > + next-level-cache = <&L2_4>; > + L2_4: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_1>; > + L3_1: l3-cache { > + compatible = "cache"; > + }; > + > + }; > + }; > + > + CPU5: cpu@10100 { > + device_type = "cpu"; > + compatible = "qcom,kryo"; > + reg = <0x0 0x10100>; > + enable-method = "psci"; > + next-level-cache = <&L2_5>; > + L2_5: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_1>; > + }; > + }; > + > + CPU6: cpu@10200 { > + device_type = "cpu"; > + compatible = "qcom,kryo"; > + reg = <0x0 0x10200>; > + enable-method = "psci"; > + next-level-cache = <&L2_6>; > + L2_6: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_1>; > + }; > + }; > + > + CPU7: cpu@10300 { > + device_type = "cpu"; > + compatible = "qcom,kryo"; > + reg = <0x0 0x10300>; > + enable-method = "psci"; > + next-level-cache = <&L2_7>; > + L2_7: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_1>; > + }; > + }; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&CPU0>; > + }; > + > + core1 { > + cpu = <&CPU1>; > + }; > + > + core2 { > + cpu = <&CPU2>; > + }; > + > + core3 { > + cpu = <&CPU3>; > + }; > + }; > + > + cluster1 { > + core0 { > + cpu = <&CPU4>; > + }; > + > + core1 { > + cpu = <&CPU5>; > + }; > + > + core2 { > + cpu = <&CPU6>; > + }; > + > + core3 { > + cpu = <&CPU7>; > + }; > + }; > + }; > + }; > + > + firmware { > + scm { > + compatible = "qcom,scm-sa8775p", "qcom,scm"; > + }; > + }; > + > + aggre1_noc: interconnect-aggre1-noc { > + compatible = "qcom,sa8775p-aggre1-noc"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + aggre2_noc: interconnect-aggre2-noc { > + compatible = "qcom,sa8775p-aggre2-noc"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + clk_virt: interconnect-clk-virt { > + compatible = "qcom,sa8775p-clk-virt"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + config_noc: interconnect-config-noc { > + compatible = "qcom,sa8775p-config-noc"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + dc_noc: interconnect-dc-noc { > + compatible = "qcom,sa8775p-dc-noc"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + gem_noc: interconnect-gem-noc { > + compatible = "qcom,sa8775p-gem-noc"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + gpdsp_anoc: interconnect-gpdsp-anoc { > + compatible = "qcom,sa8775p-gpdsp-anoc"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + lpass_ag_noc: interconnect-lpass-ag-noc { > + compatible = "qcom,sa8775p-lpass-ag-noc"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + mc_virt: interconnect-mc-virt { > + compatible = "qcom,sa8775p-mc-virt"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + mmss_noc: interconnect-mmss-noc { > + compatible = "qcom,sa8775p-mmss-noc"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + nspa_noc: interconnect-nspa-noc { > + compatible = "qcom,sa8775p-nspa-noc"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + nspb_noc: interconnect-nspb-noc { > + compatible = "qcom,sa8775p-nspb-noc"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + pcie_anoc: interconnect-pcie-anoc { > + compatible = "qcom,sa8775p-pcie-anoc"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + system_noc: interconnect-system-noc { > + compatible = "qcom,sa8775p-system-noc"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + /* Will be updated by the bootloader. */ > + memory@80000000 { > + device_type = "memory"; > + reg = <0x0 0x80000000 0x0 0x0>; > + }; > + > + qup_opp_table_100mhz: opp-table-qup100mhz { > + compatible = "operating-points-v2"; > + > + opp-100000000 { > + opp-hz = /bits/ 64 <100000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + > + reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + sail_ss_mem: sail-ss@80000000 { > + reg = <0x0 0x80000000 0x0 0x10000000>; > + no-map; > + }; > + > + hyp_mem: hyp@90000000 { > + reg = <0x0 0x90000000 0x0 0x600000>; > + no-map; > + }; > + > + xbl_boot_mem: xbl-boot@90600000 { > + reg = <0x0 0x90600000 0x0 0x200000>; > + no-map; > + }; > + > + aop_image_mem: aop-image@90800000 { > + reg = <0x0 0x90800000 0x0 0x60000>; > + no-map; > + }; > + > + aop_cmd_db_mem: aop-cmd-db@90860000 { > + compatible = "qcom,cmd-db"; > + reg = <0x0 0x90860000 0x0 0x20000>; > + no-map; > + }; > + > + uefi_log: uefi-log@908b0000 { > + reg = <0x0 0x908b0000 0x0 0x10000>; > + no-map; > + }; > + > + reserved_mem: reserved@908f0000 { > + reg = <0x0 0x908f0000 0x0 0xf000>; > + no-map; > + }; > + > + secdata_apss_mem: secdata-apss@908ff000 { > + reg = <0x0 0x908ff000 0x0 0x1000>; > + no-map; > + }; > + > + smem_mem: smem@90900000 { > + compatible = "qcom,smem"; > + reg = <0x0 0x90900000 0x0 0x200000>; > + no-map; > + hwlocks = <&tcsr_mutex 3>; > + }; > + > + cpucp_fw_mem: cpucp-fw@90b00000 { > + reg = <0x0 0x90b00000 0x0 0x100000>; > + no-map; > + }; > + > + lpass_machine_learning_mem: lpass-machine-learning@93b00000 { > + reg = <0x0 0x93b00000 0x0 0xf00000>; > + no-map; > + }; > + > + adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 { > + reg = <0x0 0x94a00000 0x0 0x800000>; > + no-map; > + }; > + > + pil_camera_mem: pil-camera@95200000 { > + reg = <0x0 0x95200000 0x0 0x500000>; > + no-map; > + }; > + > + pil_adsp_mem: pil-adsp@95c00000 { > + reg = <0x0 0x95c00000 0x0 0x1e00000>; > + no-map; > + }; > + > + pil_gdsp0_mem: pil-gdsp0@97b00000 { > + reg = <0x0 0x97b00000 0x0 0x1e00000>; > + no-map; > + }; > + > + pil_gdsp1_mem: pil-gdsp1@99900000 { > + reg = <0x0 0x99900000 0x0 0x1e00000>; > + no-map; > + }; > + > + pil_cdsp0_mem: pil-cdsp0@9b800000 { > + reg = <0x0 0x9b800000 0x0 0x1e00000>; > + no-map; > + }; > + > + pil_gpu_mem: pil-gpu@9d600000 { > + reg = <0x0 0x9d600000 0x0 0x2000>; > + no-map; > + }; > + > + pil_cdsp1_mem: pil-cdsp1@9d700000 { > + reg = <0x0 0x9d700000 0x0 0x1e00000>; > + no-map; > + }; > + > + pil_cvp_mem: pil-cvp@9f500000 { > + reg = <0x0 0x9f500000 0x0 0x700000>; > + no-map; > + }; > + > + pil_video_mem: pil-video@9fc00000 { > + reg = <0x0 0x9fc00000 0x0 0x700000>; > + no-map; > + }; > + > + hyptz_reserved_mem: hyptz-reserved@beb00000 { > + reg = <0x0 0xbeb00000 0x0 0x11500000>; > + no-map; > + }; > + > + tz_stat_mem: tz-stat@d0000000 { > + reg = <0x0 0xd0000000 0x0 0x100000>; > + no-map; > + }; > + > + tags_mem: tags@d0100000 { > + reg = <0x0 0xd0100000 0x0 0x1200000>; > + no-map; > + }; > + > + qtee_mem: qtee@d1300000 { > + reg = <0x0 0xd1300000 0x0 0x500000>; > + no-map; > + }; > + > + trusted_apps_mem: trusted-apps@d1800000 { > + reg = <0x0 0xd1800000 0x0 0x3900000>; > + no-map; > + }; > + }; > + > + soc: soc@0 { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges = <0 0 0 0 0x10 0>; > + > + gcc: clock-controller@100000 { > + compatible = "qcom,sa8775p-gcc"; > + reg = <0x0 0x100000 0x0 0xc7018>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&sleep_clk>, > + <0>, > + <0>, > + <0>, > + <0>, > + <0>, > + <0>, > + <0>, > + <0>, > + <0>, > + <0>, > + <0>, > + <0>, > + <0>; > + power-domains = <&rpmhpd SA8775P_CX>; > + }; > + > + ipcc: mailbox@408000 { > + compatible = "qcom,sa8775p-ipcc", "qcom,ipcc"; > + reg = <0x0 0x408000 0x0 0x1000>; > + interrupts = ; > + interrupt-controller; > + #interrupt-cells = <3>; > + #mbox-cells = <2>; > + }; > + > + qupv3_id_1: geniqup@ac0000 { > + compatible = "qcom,geni-se-qup"; > + reg = <0x0 0xac0000 0x0 0x6000>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + clock-names = "m-ahb", "s-ahb"; > + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, > + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; > + iommus = <&apps_smmu 0x443 0x0>; > + status = "disabled"; > + > + uart10: serial@a8c000 { > + compatible = "qcom,geni-uart"; > + reg = <0x0 0xa8c000 0x0 0x4000>; > + interrupts = ; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; > + interconnect-names = "qup-core", "qup-config"; > + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 > + &clk_virt SLAVE_QUP_CORE_1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 > + &config_noc SLAVE_QUP_1 0>; > + power-domains = <&rpmhpd SA8775P_CX>; > + operating-points-v2 = <&qup_opp_table_100mhz>; > + status = "disabled"; > + }; > + }; > + > + intc: interrupt-controller@17a00000 { > + compatible = "arm,gic-v3"; > + reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ > + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ > + interrupt-controller; > + #interrupt-cells = <3>; > + interrupts = ; > + #redistributor-regions = <1>; > + redistributor-stride = <0x0 0x20000>; > + }; > + > + memtimer: timer@17c20000 { > + compatible = "arm,armv7-timer-mem"; > + reg = <0x0 0x17c20000 0x0 0x1000>; > + ranges = <0x0 0x0 0x0 0x20000000>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + frame@17c21000 { > + reg = <0x17c21000 0x1000>, > + <0x17c22000 0x1000>; > + interrupts = , > + ; > + frame-number = <0>; > + }; > + > + frame@17c23000 { > + reg = <0x17c23000 0x1000>; > + interrupts = ; > + frame-number = <1>; > + status = "disabled"; > + }; > + > + frame@17c25000 { > + reg = <0x17c25000 0x1000>; > + interrupts = ; > + frame-number = <2>; > + status = "disabled"; > + }; > + > + frame@17c27000 { > + reg = <0x17c27000 0x1000>; > + interrupts = ; > + frame-number = <3>; > + status = "disabled"; > + }; > + > + frame@17c29000 { > + reg = <0x17c29000 0x1000>; > + interrupts = ; > + frame-number = <4>; > + status = "disabled"; > + }; > + > + frame@17c2b000 { > + reg = <0x17c2b000 0x1000>; > + interrupts = ; > + frame-number = <5>; > + status = "disabled"; > + }; > + > + frame@17c2d000 { > + reg = <0x17c2d000 0x1000>; > + interrupts = ; > + frame-number = <6>; > + status = "disabled"; > + }; > + }; > + > + apps_rsc: rsc@18200000 { > + compatible = "qcom,rpmh-rsc"; > + reg = <0x0 0x18200000 0x0 0x10000>, > + <0x0 0x18210000 0x0 0x10000>, > + <0x0 0x18220000 0x0 0x10000>; > + reg-names = "drv-0", "drv-1", "drv-2"; > + interrupts = , > + , > + ; > + qcom,tcs-offset = <0xd00>; > + qcom,drv-id = <2>; > + qcom,tcs-config = , > + , > + , > + ; > + label = "apps_rsc"; > + > + apps_bcm_voter: bcm-voter { > + compatible = "qcom,bcm-voter"; > + }; > + > + rpmhcc: clock-controller { > + compatible = "qcom,sa8775p-rpmh-clk"; > + #clock-cells = <1>; > + clock-names = "xo"; > + clocks = <&xo_board_clk>; > + }; > + > + rpmhpd: power-controller { > + compatible = "qcom,sa8775p-rpmhpd"; > + #power-domain-cells = <1>; > + operating-points-v2 = <&rpmhpd_opp_table>; > + > + rpmhpd_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + rpmhpd_opp_ret: opp-0 { > + opp-level = ; > + }; > + > + rpmhpd_opp_min_svs: opp-1 { > + opp-level = ; > + }; > + > + rpmhpd_opp_low_svs: opp2 { > + opp-level = ; > + }; > + > + rpmhpd_opp_svs: opp3 { > + opp-level = ; > + }; > + > + rpmhpd_opp_svs_l1: opp-4 { > + opp-level = ; > + }; > + > + rpmhpd_opp_nom: opp-5 { > + opp-level = ; > + }; > + > + rpmhpd_opp_nom_l1: opp-6 { > + opp-level = ; > + }; > + > + rpmhpd_opp_nom_l2: opp-7 { > + opp-level = ; > + }; > + > + rpmhpd_opp_turbo: opp-8 { > + opp-level = ; > + }; > + > + rpmhpd_opp_turbo_l1: opp-9 { > + opp-level = ; > + }; > + }; > + }; > + }; > + > + tcsr_mutex: hwlock@1f40000 { > + compatible = "qcom,tcsr-mutex"; > + reg = <0x0 0x1f40000 0x0 0x20000>; > + #hwlock-cells = <1>; > + }; > + > + tlmm: pinctrl@f000000 { > + compatible = "qcom,sa8775p-tlmm"; > + reg = <0x0 0xf000000 0x0 0x1000000>; > + interrupts = ; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + gpio-ranges = <&tlmm 0 0 149>; > + }; > + > + apps_smmu: iommu@15000000 { > + compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; > + reg = <0x0 0x15000000 0x0 0x100000>; > + #iommu-cells = <2>; > + #global-interrupts = <2>; > + > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + }; > + }; > + > + arch_timer: timer { > + compatible = "arm,armv8-timer"; > + interrupts = , > + , > + , > + ; > + }; > +};